Datasheet

MAX4521/MAX4522/MAX4523
Quad, Low-Voltage, SPST Analog Switches
_______________________________________________________________________________________ 9
V
GEN
GND
NC or
NO
C
L
V
OUT
V-
V-
V+
V
OUT
IN
OFF
ON
OFF
ΔV
OUT
Q = (ΔV
OUT
)(C
L
)
COM
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
OFF
ON
OFF
IN
V
IN
= +3V
V+
R
GEN
IN
MAX4521
MAX4522
MAX4523
Figure 3. Charge Injection
50%
0.9 x V
0UT1
+3V
0
0
LOGIC
INPUT
SWITCH
OUTPUT 2
(V
OUT2
)
0
0.9 x V
OUT2
t
D
t
D
LOGIC
INPUT
V-
V-
R
L2
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
COM2
IN1, 2
COM1
V
OUT2
V+
V+
C
L2
V
COM1
R
L1
V
OUT1
C
L1
R
L
= 300Ω
C
L
= 35pF
NO
NC
SWITCH
OUTPUT 1
(V
OUT1
)
MAX4523
V
COM2
Figure 1. Switching Time
Figure 2. Break-Before-Make Interval (MAX4523 only)
Test Circuits/Timing Diagrams
t
r
< 20ns
t
f
< 20ns
50%
0
LOGIC
INPUT
V-
V-
R
L
300Ω
NO
or NC
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
COM (
R
L
)
R
L
+ R
ON
SWITCH
INPUT
IN, EN
+3V
t
OFF
0
COM
SWITCH
OUTPUT
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR EN AND SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
C
L
35pF
V+
V+
V
OUT
V
COM
0
MAX4521
MAX4522
MAX4523