Datasheet

MAX3984
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
14 ______________________________________________________________________________________
Layout Considerations
Circuit board layout and design can significantly affect
the performance of the MAX3984. Use good high-fre-
quency design techniques, including minimizing
ground inductance and using controlled-impedance
transmission lines on the data signals. Power-supply
decoupling should also be placed as close as possible
to the V
CC
pins. Always connect all V
CC
pins to a
power plane. Take care to isolate the input from the
output signals to reduce feed through.
Exposed-Pad Package
The exposed-pad, 16-pin thin QFN package incorpo-
rates features that provide a very low thermal resis-
tance path for heat removal from the IC. The exposed
pad on the MAX3984 must be soldered to the circuit
board for proper thermal performance. Refer to Maxim
Application Note HFAN-08.1: Thermal Considerations
of QFN and Other Exposed-Paddle Packages for addi-
tional information.
GND
50Ω
50Ω
IN+
IN-
V
CC1
V
CC1
- 1.5V
OUT+
OUT-
GND
50Ω
50Ω
V
CC2
GND
LVTTL IN
V
CCX
R
PULLUP
PIN NAME
V
CCX
V
CC1
V
CC2
V
CC2
R
PULLUP
(kΩ)
40
20
10
IN_LEV
OUT_LEV
TX_DISABLE, PE0, PE1
Figure 7. LVTTL Equivalent Input Structure
LOS
GND
Figure 8. Loss-of-Signal Equivalent Output Structure
Figure 5. IN+/IN- Equivalent Input Structure
Interface Schematics
Figure 6. OUT+/OUT- Equivalent Output Structure