Datasheet

MAX3969
200Mbps SFP Limiting Amplifier
4 _______________________________________________________________________________________
10μs/div
POWER-DETECT TIMING WITH SQUELCH
(INPUT = 12mV
P-P
, C
FILTER
= 0.01μF,
R2 = 15kΩ, 155Mbps, 2
23
- 1 PRBS)
IN
MAX3969 toc10
OUT
LOS
SD
PULSE-WIDTH DISTORTION
vs. DIFFERENTIAL INPUT VOLTAGE
MAX3969 toc11
DIFFERENTIAL INPUT VOLTAGE (mV
P-P
)
PULSE-WIDTH DISTORTION (ps)
100010010
10
20
30
40
50
60
70
80
90
100
0
1 10,000
100Mbps
1-0 PATTERN
INPUT DATA THROUGH
117MHz FILTER
UNFILTERED
INPUT DATA
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
-40 -15 10 35 60 85
DATA OUTPUT TRANSITION TIME
vs. TEMPERATURE
MAX3969 toc12
AMBIENT TEMPERATURE (°C)
TRANSITION TIME (ns)
Typical Operating Characteristics (continued)
(V
CC
= +3.3V, PECL outputs terminated with 50Ω to V
CC
- 2V, R1 = 100kΩ, T
A
= +25°C, unless otherwise noted.)
Pin Description
PIN NAME FUNCTION
1 INV
Inverting Input of Internal Op Amp that Sets Power-Detect Threshold Voltage (Figure 1). Connect a
resistor from V
TH
to INV (R2), and from INV to ground (R1 = 100kΩ), to program the desired threshold
voltage.
2 FILTER
Filter Output of Logarithmic Full-Wave Detectors (FWDs). The FWD outputs are summed together at
FILTER to generate the RSSI output. Connect a capacitor from FILTER to V
CC
for proper operation.
3 RSSI
Received-Signal-Strength Indicator Output. The voltage at RSSI indicates the input-signal power. The
RSSI output is reduced approximately 120mV when LOS is asserted.
4 IN- Inverting Data Input
5 IN+ Noninverting Data Input
6 , 7, 8 GND Ground
9 CZP Autozero Capacitor Input. Connect a capacitor between CZP and CZN.
10 CZN Autozero Capacitor Input. Connect a capacitor between CZP and CZN.
11 V
CCO
Output-Buffer Supply Voltage. Connect to the same potential as V
CC
.
12 OUT+ Noninverting PECL Data Output. Terminate with 50Ω to (V
CC
- 2V).
13 OUT- Inverting PECL Data Output. Terminate with 50Ω to (V
CC
- 2V).
14 SD
Signal Detect, PECL Output. The SD output is high when input power is above the power-detect
threshold, and low when input power is below the power-detect threshold. This pin is PECL-
compatible and should be terminated with 50Ω to (V
CC
- 2V) or equivalent.
15 LOS
Loss-of-Signal Output, TTL Open Collector (with ESD Protection). The LOS output is high when input
power is below the power-detect threshold, and low when input power is above the power-detect
threshold.
16 LOS
Inverted Loss-of-Signal Output, TTL Open Collector (with ESD Protection). The LOS output is low
when input power is below the power-detect threshold, and high when input power is above the
power-detect threshold.