Datasheet

MAX394
Low-Voltage, Quad, SPDT,
CMOS Analog Switch
10 ______________________________________________________________________________________
50%
V
O1
V
O2
0.9V
O
+3V
0V
V
COM
0V
V
COM
LOGIC
INPUT
SWITCH
OUTPUT
SWITCH
OUTPUT
+5V
V+
NO
V-
-5V
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
LOGIC 0 INPUT.
GND
LOGIC
INPUT
0V
0.9V
O
t
D
t
D
R
L2
NC
C
L2
V
O2
V
O1
C
L1
R
L
= 1kΩ
C
L
= 35pF
COM_
V
COM
R
L1
IN_
MAX394
Figure 5. Break-Before-Make Delay
t
R
< 20ns
t
F
< 20ns
50%
0V
+10V
LOGIC
INPUT
V-
-15V
300Ω
COM_
GND
(REPEAT TEST FOR IN2, IN3, AND IN4.)
V
IN
+10V
IN_
NO_
50%
t
OPEN
50% 50%
50% 50%
3V
t
OPEN
t
ON
t
OFF
t
ON
t
OFF
0V
-10V
V
COM
+15V
V+
NC_
-10V
SWITCH OUTPUT
MAX394
V-
CAPACITANCE
METER
GND
C
-5V
IN
0V or 2.4V
C
+5V
V+
NC
or NO
COM
MAX394
Figure 2. Switching-Time Test Circuit
Figure 3. Channel Off-Capacitance
V-
CAPACITANCE
METER
GND
C
-5V
IN
0V or 2.4V
C
+5V
V+
COM
NC or
NO
MAX394
Figure 4. Channel On-Capacitance
______________________________________________Test Circuits/Timing Diagrams