Datasheet

_______________________________________________________________________________________ 5
MAX3946
1Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +2.85V to +3.63V, T
A
= -40°C to +85°C, and Figure 1. Guaranteed by design and characterization from T
A
= -40°C to +95°C.
Typical values are at V
CC
= +3.3V, I
BIAS
= 60mA, I
MOD
= 40mA, 25I differential output load, and T
A
= +25°C, unless otherwise
noted.) (Note 2)
Note 2: Guaranteed by design and characterization (T
A
= -40NC to +95NC).
Note 3: BIAS is connected to 2.0V. TOUT+/TOUT- are connected through pullup inductors to a separate supply that is equal to V
CCT
.
Note 4: Stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and V
CC
=
V
CCREF
Q5%. V
CCREF
= 3.0V to 3.45V. Reference current measured at V
CCREF
, T
A
= +25NC.
Note 5: Measured with K28.5 data pattern at 10.7Gbps and with a (2
7
- 1 PRBS + 72 zeros + 2
7
- 1 PRBS (inverted) + 72 ones)
pattern at 11.3Gbps.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CONTROL I/O SPECIFICATIONS
DISABLE Input Current
I
IH
12
FA
I
IL
Depends on pullup resistance 500 800
DISABLE Input High Voltage V
IH
1.8 V
CC
V
DISABLE Input Low Voltage V
IL
0 0.8 V
DISABLE Input Resistance R
PULL
Internal pullup resistor 4.7 7.5 10
kI
3-WIRE DIGITAL I/O SPECIFICATIONS (SDA, SCL, CSEL)
Input High Voltage V
IH
2.0 V
CC
V
Input Low Voltage V
IL
0.8 V
Input Hysteresis V
HYST
80 mV
Input Leakage Current I
IL
, I
IH
V
IN
= 0V or V
CC
, internal pullup or
pulldown is 75kI typical
150
FA
Output High Voltage V
OH
External pullup is (4.7kI to 10kI) to V
CC
V
CC
- 0.5 V
Output Low Voltage V
OL
External pullup is (4.7kI to 10kI) to V
CC
0.4 V
3-WIRE DIGITAL INTERFACE TIMING CHARACTERISTICS (Figure 5)
SCL Clock Frequency f
SCL
400 1000 kHz
SCL Pulse-Width High t
CH
0.5
Fs
SCL Pulse-Width Low t
CL
0.5
Fs
SDA Setup Time t
DS
100 ns
SDA Hold Time t
DH
100 ns
SCL Rise to SDA Propagation
Time
t
D
5 ns
CSEL Pulse-Width Low t
CSW
500 ns
CSEL Leading Time Before the
First SCL Edge
t
L
500 ns
CSEL Trailing Time After the Last
SCL Edge
t
T
500 ns
SDA, SCL Load C
B
Total bus capacitance on one line with
4.7kI pullup to V
CC
20 pF