Datasheet

24 _____________________________________________________________________________________
MAX3946
1Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Table 6. Register Summary (continued)
REGISTER
FUNCTION/
ADDRESS
REGISTER
NAME
NORMAL
MODE
SETUP
MODE
BIT
NUMBER/
TYPE
BIT NAME
DEFAULT
VALUE
NOTES
Modulation
Current
Increment
Setting Register
Address =
H0x0C
MODINC
R R 7 SET_IMOD[0] 0
LSB of SET_IMOD DAC
register address = H0x09
RW RW 4 MODINC[4] 0
MSB MOD DAC two’s
complement
RW RW 3 MODINC[3] 0
RW RW 2 MODINC[2] 0
RW RW 1 MODINC[1] 0
RW RW 0 MODINC[0] 0
LSB MOD DAC two’s
complement
Bias Current
Increment
Setting Register
Address =
H0x0D
BIASINC
R R 7 SET_IBIAS[0] 0
LSB of SET_IBIAS DAC
register address = H0x08
RW RW 4 BIASINC[4] 0
MSB bias DAC two’s
complement
RW RW 3 BIASINC[3] 0
RW RW 2 BIASINC[2] 0
RW RW 1 BIASINC[1] 0
RW RW 0 BIASINC[0] 0
LSB bias DAC two’s
complement
Mode Control
Register
Address =
H0x0E
MODECTRL
RW RW 7 MODECTRL[7] 0
MSB mode control
RW RW 6 MODECTRL[6] 0
RW RW 5 MODECTRL[5] 0
RW RW 4 MODECTRL[4] 0
RW RW 3 MODECTRL[3] 0
RW RW 2 MODECTRL[2] 0
RW RW 1 MODECTRL[1] 0
RW RW 0 MODECTRL[0] 0
LSB mode control
Pulse-Width
Control Register
Address =
H0x0F
SET_
PWCTRL
R RW 3 SET_PWCTRL[3] 0
MSB Tx pulse-width
control
R RW 2 SET_PWCTRL[2] 0
R RW 1 SET_PWCTRL[1] 0
R RW 0 SET_PWCTRL[0] 0
LSB Tx pulse-width con-
trol
Deemphasis
Control Register
Address = H0x10
SET_TXDE
R RW 5 SET_TXDE[5] 0
MSB Tx deemphasis
R RW 4 SET_TXDE[4] 0
R RW 3 SET_TXDE[3] 0
R RW 2 SET_TXDE[2] 0
R RW 1 SET_TXDE[1] 0
R RW 0 SET_TXDE[0] 1
LSB Tx deemphasis
Equalization
Control Register
Address = H0x11
SET_TXEQ
R RW 2 SET_TXEQ[2] 0
Tx equalization
R RW 1 SET_TXEQ[1] 0