Datasheet

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MAX3946
1Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Transmitter Control Register (TXCTRL)
Bits 5 and 4: TXDE_MD[1:0]. Controls the mode of the transmit output deemphasis circuitry.
00 = deemphasis is fixed at 6.25% of the modulation amplitude
01 = deemphasis is fixed at 3.125% of the modulation amplitude
10 = deemphasis is programmed by the SET_TXDE register setting
11 = deemphasis is at its maximum of approximately 9%
Bit 3: TXEQ_EN. Enables or disables the input equalization circuitry.
0 = disabled
1 = enabled
Bit 2: SOFTRES. Resets all registers to their default values (the DISABLE pin must be at a logic 1 during a write to
SOFTRES for the registers to be set to their default values).
0 = normal
1 = reset
Bit 1: TX_POL. Controls the polarity of the signal path.
0 = inverse
1 = normal
Bit 0: TX_EN. Enables or disables the output circuitry.
0 = disabled
1 = enabled
Figure 5. Timing for 3-Wire Digital Interface
CSEL
SCL
SDA
CSEL
SCL
SDA
1 2 3 4 5 6 7 8
A6
9 10 11 12 13 14 150
1 2 3 4 5 6 7 8 9 10 11 12 13 14 150
A5 A4 A3 A2 A1 RWN D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0RWN
WRITE MODE
READ MODE
A0
A6 A5 A4 A3 A2 A1 A0
t
L
t
L
t
CH
t
CL
t
DS
t
DH
t
CH
t
CL
t
DS
t
D
t
DH
t
T
t
T
Bit #
7 6 5 4 3 2 1 0 ADDRESS
Name X X TXDE_MD[1] TXDE_MD[0] TXEQ_EN SOFTRES TX_POL TX_EN
H0x05
Default Value X X 0 0 0 0 1 1