Datasheet

______________________________________________________________________________________ 11
MAX3946
1Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Pin Description (continued)
Figure 2. Functional Diagram
EYE SAFETY AND
OUTPUT CONTROL
TOUT+
V
CCT
TOUT-
BIAS
BMON
TX_EN
TX_POL
50I50I
FAULT
TIN+
TIN-
SDA
SCL
CSEL
DISABLE
BMAX
LASER BIAS
CURRENT LIMITER
POWER-ON RESET
V
CCD
7.5kI
V
CCD
V
EET
V
EET
V
CM
75kI
1
0
PW
CONTROL
25I
25I
EQ
I
MOD_DAC
+ I
DE_DAC
I
BIAS
V
CC
I
BIAS
100
3-WIRE
INTERFACE
REGISTER
CONTROL
LOGIC
SET_TXEQ
SET_PWCTRL
75kI 75kI
9b DAC SET_IMOD
6b DAC SET_TXDE
9b DAC SET_IBIAS
MAX3946
PIN NAME FUNCTION
18 SCL
Serial-Clock Input, CMOS. This pin has a 75kI internal pulldown.
19, 24 V
EET
Ground
20, 23 V
CC
Power-Supply Connections. Provides supply voltage to the core circuitry.
21 TIN+ Noninverted Data Input
22 TIN- Inverted Data Input
— EP
Exposed Pad. Ground. Must be soldered to circuit board ground for proper thermal and electrical
performance (see the Exposed-Pad Package and Thermal Considerations section).