Datasheet
10 _____________________________________________________________________________________
MAX3946
1Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Pin Configuration
Pin Description
23
24
22
21
8
7
9
DISABLE
BMAX
BMON
V
CCT
10
V
CCD
SDA
V
CCD
BIAS
SCL
V
CCT
1 2
TIN-
4 5 6
1718 16 14 13
V
CC
V
EET
TOUT+
TOUT-
TOUT-
V
CCT
MAX3946
FAULT
CSEL
3
15
TIN+
20
11
TOUT+
V
CC
19
12
V
CCT
V
EET
THIN QFN
(4mm × 4mm)
TOP VIEW
+
*EP
*EXPOSED PAD CONNECTED TO GROUND.
PIN NAME FUNCTION
1, 15 V
CCD
Power Supply. Provides supply voltage to the digital block.
2 DISABLE
Disable Input, CMOS. Set to logic-low for normal operation. Logic-high or open disables both the
modulation current and the bias current. Internally pulled up by a 7.5kI resistor to V
CCD
.
3 FAULT
Fault Output, Open Drain. Logic-high indicates a fault condition. FAULT remains high even after the
fault condition has been removed. A logic-low occurs when the fault condition has been removed and
the fault latch has been cleared by toggling the DISABLE pin. FAULT should be pulled up to V
CC
by
a 4.7kI to 10kI resistor.
4 BMAX
Analog Laser Bias-Current Limit. A resistive voltage-divider connected among BMON, BMAX, and
ground sets the maximum allowed laser bias current limit. The voltage at BMAX is internally com-
pared to 1.2V bandgap reference voltage.
5 BMON
Bias Current-Monitor Output. Current out of this pin develops a ground-referenced voltage across
external resistor(s) that is proportional to the laser bias current. The current sourced by this pin is
typically 1/100th the BIAS pin current.
6, 7, 12, 13 V
CCT
Power Supply. Provides supply voltage to the output block.
8, 9 TOUT-
Inverted Modulation Current Output. Internally pulled up by a 25I resistor to V
CCT
.
10, 11 TOUT+
Noninverted Modulation Current Output. Internally pulled up by a 25I resistor to V
CCT
.
14 BIAS Laser Bias Current Connection. This pin requires a 0.1µF capacitor to V
EET
for proper operation.
16 CSEL
Chip-Select Input, CMOS. Setting CSEL to logic-high starts a cycle. Setting CSEL to logic-low ends
the cycle and resets the control state machine. Internally pulled down by a 75kI resistor to V
EET
.
17 SDA
Serial-Data Bidirectional Input, CMOS. Open-drain output. This pin has a 75kI internal pullup, but it
requires an external 4.7kI to 10kI pullup resistor. (Data line-collision protection is implemented.)