Datasheet

6 ______________________________________________________________________________________
MAX3945
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100I load, C
CAZ
= 0.1FF, T
A
= -40NC to +85NC. Registers
are set to default values, unless otherwise noted. Typical values are at V
CC
= 3.3V, T
A
= +25NC, unless otherwise noted.)
Note 1: Guaranteed by design and characterization, T
A
= -40NC to +95NC.
Note 2: Deterministic jitter is measured with a repeating K28.5 pattern [00111110101100000101] for 1.25Gbps to 8.5Gbps data.
At 10.32Gbps and 11.3Gbps, a repeating K28.5 plus 59 0s and K28.5 plus 59 1s pattern is used. Deterministic jitter is
defined as the arithmetic sum of pulse-width distortion (PWD) and pattern-dependent jitter (PDJ).
Note 3: LOS1_EN = 1, data rates of 1.25Gbps to 8.5Gbps with K28.5 pattern, and 6.4GHz input filter. For data rates of 10.32Gbps
to 11.3Gbps, the input filter is 12.5GHz and the pattern is PRBS23-1.
Note 4: Measurement includes an input AC-coupling capacitor of 100nF and C
CAZ
of 100nF. The signal at the RIN or RPMIN input
is switched between two amplitudes: Signal_ON and Signal_OFF.
1) Receiver operates at sensitivity level plus 1dB power penalty
a) Signal_OFF = 0
Signal_ON = (+8dB) + 10log(min_assert_level)
b) Signal_ON = (+1dB) + 10log(max_deassert_level)
Signal_OFF = 0
2) Receiver operates at overload
Signal_OFF = 0
Signal_ON = 1.2V
P-P
max_deassert_level and min_assert_level are measured for one SET_LOS setting
Note 5: LOS1_EN = 0, LOS2_EN = 1, DC voltage applied to the RPMIN input.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CSEL Leading Time Before the
First SCL Edge
t
L
500 ns
CSEL Trailing Time After the Last
SCL Edge
t
T
500 ns
SDA, SCL External Load C
B
Total bus capacitance on one line with
4.7kI to V
CC
20 pF