Datasheet

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MAX3945
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Design Procedure
Programming CML Output Levels
See Tables 13 and 14. For each value of the bits
RXDE1 and RXDE0 in Table 13, the value of deempha-
sis does vary with the SET_CML[7:0] setting. In Table
13, the values of deemphasis are given for the setting
SET_CML[7:0] = 120d. The variation of deemphasis for
other values of SET_CML[7:0] is shown in the Typical
Operating Characteristics (see the Deemphasis Value
vs. SET_CML DAC Setting (RATE_SEL = 1) graph). Note
that even though RXDE_EN = 0, there is still some deem-
phasis for RATE_SEL = 1 for values of amplitude control below
SET_CML[7:0] = 170d.
Select the Coupling Capacitor
For AC-coupling, the coupling capacitors C
IN
and C
OUT
should be selected to minimize the receiver’s determin-
istic jitter. Jitter is decreased as the input low frequency
cutoff (f
IN
) is decreased: f
IN
= 1/[2G(50)(C
IN
)]. The
recommended value of C
IN
and C
OUT
is 0.1FF for the
MAX3945.
Select the Offset-Correction Capacitor
The capacitor between CAZ and ground determines the
time constant of the signal path DC-offset cancellation
loop. A 0.1FF capacitor between CAZ and ground is
recommended for the MAX3945.
Applications Information
Layout Considerations
Use good, high-frequency layout techniques and mul-
tiple-layer boards with uninterrupted ground planes to
minimize EMI and crosstalk.
Exposed-Pad Package
The exposed pad on the 16-pin TQFN provides a very
low-thermal resistance path for heat removal from the IC.
The pad is also electrical ground on the MAX3945 and
must be soldered to the circuit board ground for proper
thermal and electrical performance. Refer to Application
Note 862: HFAN-08.1: Thermal Considerations of QFN
and Other Exposed-Paddle Packages for additional
information.
Table 13. CML Output Amplitude Equations (Typical)
Table 14. SET_CML DAC Codes for 400mV
P-P
and 800mV
P-P
Output Levels
RXCTRL1[1] RXCTRL2[1] RXCTRL1[7:6]
DEEMPHASIS (dB)
(SET_CML[7:0] = 120d)
EQUATION FOR (V
ROUT+
- V
ROUT-
)
RATE_SEL RXDE_EN RXDE1 RXDE0
0 X X X 0 45mV
P-P
+ 4.5mV
P-P
x SET_CML
1 0 X X 0.72 4.5mV
P-P
x SET_CML
1 1 0 0 1.17 -4mV
P-P
+ 4.1mV
P-P
x SET_CML
1 1 0 1 1.89 -7mV
P-P
+ 3.9mV
P-P
x SET_CML
1 1 1 0 2.48 -10mV
P-P
+ 3.6mV
P-P
x SET_CML
1 1 1 1 3.86 -13mV
P-P
+ 3.3mV
P-P
x SET_CML
RXCTRL1[1] RXCTRL2[1] RXCTRL1[7:6] SET_CML DAC CODE
RATE_SEL RXDE_EN RXDE1 RXDE0 400mV
P-P
800mV
P-P
0 X X X 80 169
1 0 X X 91 181
1 1 0 0 98 194
1 1 0 1 106 208
1 1 1 0 115 225
1 1 1 1 126 245