Datasheet

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MAX3945
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Receiver Status Register (RXSTAT)
Bit 1: POR_2d. When the V
CC
supply voltage is below 2.3V, the POR circuitry sets POR_2d high. When the supply
voltage is above 2.75V, the POR circuitry deasserts, but the POR_2d bit remains high until it is read.
Bit 0: LOS_2d. Copy of the LOS status. This is a sticky bit, which means that it is cleared on a read. The first 0-to-1
transition is latched until the bit is read by the master or POR occurs.
CML Output Level Setting Register (SET_CML)
Bits 7 to 0: SET_CML[7:0]. The SET_CML register is an 8-bit register that can be set up to 255 for maximum CML
output amplitude. See Table 13 for equations to determine CML output level vs. SET_CML.
LOS Threshold Assert Level Setting Register (SET_LOS)
Bits 5 to 0: SET_LOS[5:0]. The SET_LOS register is a 6-bit register used to program the LOS threshold. See the
Typical Operating Characteristics section for a typical LOS threshold voltage vs. DAC code for both the Rx input-based
LOS and the RSSI monitor-based LOS.
Bit #
7 6 5 4 3 2
1
(STICKY)
0
(STICKY)
ADDRESS
Name X X X X X X POR_2d LOS_2d
H0x02
Default Value X X X X X X X X
Bit #
7 6 5 4 3 2 1 0 ADDRESS
Name
SET_CML[7]
(MSB)
SET_CML[6] SET_CML[5] SET_CML[4] SET_CML[3] SET_CML[2] SET_CML[1]
SET_CML[0]
(LSB)
H0x03
Default Value 0 1 0 1 1 1 0 0
Bit #
7 6 5 4 3 2 1 0 ADDRESS
Name X X
SET_LOS[5]
(MSB)
SET_LOS[4] SET_LOS[3] SET_LOS[2] SET_LOS[1]
SET_LOS[0]
(LSB)
H0x04
Default Value X X 0 0 1 1 0 0