Datasheet

18 _____________________________________________________________________________________
MAX3945
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Receiver Control Register 2 (RXCTRL2)
Bit 7: LOS2_EN. Enables or disables the RSSI monitor-based LOS circuitry, in combination with the LOS1_EN bit. The
below table shows when the RSSI monitor-based LOS is disabled and enabled.
Bit 6: LOS1_EN. Controls the Rx input-based LOS circuitry. When RX_EN is set to 0, the LOS detector is also disabled.
0 = disabled
1 = enabled
Bit 5: LOS_POL. Controls the polarity of the LOS pin.
0 = inverse
1 = normal
Bit 4: RX_POL. Controls the polarity of the CML output.
0 = inverse
1 = normal
Bit 3: SQ_EN. When SQ_EN = 1, the CML output is squelched when LOS is asserted.
0 = disabled
1 = enabled
Bit 2: RX_EN. Enables or disables the receive circuitry.
0 = disabled
1 = enabled
Bit 1: RXDE_EN. Enables or disables the deemphasis on the CML output.
0 = disabled
1 = enabled
Bit 0: AZ_EN. Enables or disables the autozero circuitry.
0 = disabled
1 = enabled
Bit #
7 6 5 4 3 2 1 0 ADDRESS
Name LOS2_EN LOS1_EN LOS_POL RX_POL SQ_EN RX_EN RXDE_EN AZ_EN
H0x01
Default Value 0 1 1 1 0 1 0 1
LOS2_EN LOS1_EN RX_EN Rx INPUT-BASED LOS RSSI MONITOR-BASED LOS
0 0 X Disabled and powered down Disabled and powered down
0 1 1 Enabled Disabled and powered down
X 1 0 Disabled and powered down Disabled and powered down
1 1 1 Enabled Disabled and powered down
1 0 0 Disabled and powered down Enabled
1 0 1 Disabled and powered down Enabled