Datasheet

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MAX3945
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Register Descriptions
Receiver Control Register 1 (RXCTRL1)
Bits 7 and 6: RXDE[1:0]. These 2 bits are used to control deemphasis of the output waveform. See Table 5 for the bit
settings and corresponding deemphasis levels.
Bit 4: SOFTRES. When this bit is set to 1 during a 3-wire interface write operation, all registers are set to the default
state when CSEL goes low.
Bits 3 and 2: BW[1:0]. When RATE_SEL = 0, these 2 bits control the bandwidth of the limiting amplifier. See Table 1 for
the settings and corresponding filter selection.
Bit 1: RATE_SEL. RATE_SEL selects between the low bandwidth data path (1.0625Gbps to 4.25Gbps) and the high
bandwidth data path (4.25Gbps to 11.3Gbps). When RATE_SEL is set to 1, the high bandwidth path is chosen. When
RATE_SEL is set to 0, the low bandwidth path is chosen.
Figure 5. Timing for the 3-Wire Digital Interface
Table 11. Interface Timing Parameters
*Do not change default setting.
CSEL
SCL
SDA
CSEL
SCL
SDA
1 2 3 4 5 6 7 8
A6
9 10 11 12 13 14 150
1 2 3 4 5 6 7 8 9 10 11 12 13 14 150
A5 A4 A3 A2 A1 RWN D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0RWN
WRITE MODE
READ MODE
A0
A6 A5 A4 A3 A2 A1 A0
t
L
t
L
t
CH
t
CL
t
DS
t
DH
t
CH
t
CL
t
DS
t
D
t
DH
t
T
t
T
SYMBOL DEFINITION
t
L
CSEL leading time before the first SCL edge
t
CH
SCL pulse-width high
t
CL
SCL pulse-width low
t
D
SCL rise to SDA propagation time
t
DS
SDA setup time
t
DH
SDA hold time
t
T
CSEL trailing time after last SCL edge
Bit #
7 6 5 4 3 2 1 0 ADDRESS
Name RXDE1 RXDE0 X* SOFTRES BW1 BW0 RATE_SEL X*
H0x00
Default Value 0 0 1 0 1 1 1 1