Datasheet

16 _____________________________________________________________________________________
MAX3945
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
3-Wire Digital Communication
General
The MAX3945 implements a proprietary 3-wire digital
interface. An external controller generates the clock. The
3-wire interface consists of an SDA bidirectional data
line, an SCL clock signal input, and a CSEL chip-select
input (active high). The external master initiates a data
transfer by asserting the CSEL pin. The master starts to
generate a clock signal after the CSEL has been set to
1. All data transfers are most significant bit (MSB) first.
Protocol
Each operation consists of 16-bit transfers (15-bit
address/data, 1-bit RWN). The bus master generates 16
clock cycles to SCL. All operations transfer 8 bits to the
MAX3945. The RWN bit determines if the cycle is read
or write. See Table 9.
Register Addresses
The MAX3945 contains seven registers available for pro-
gramming. Table 10 shows the registers and addresses.
Write Mode (RWN = 0)
The master generates 16 total clock cycles at SCL. The
master outputs a total of 16 bits (MSB first) to the SDA
line at falling edge of the clock. The master closes the
transmission by setting CSEL to 0. Figure 5 shows the
interface timing, and Table 11 defines the various timing
parameters.
Read Mode (RWN = 1)
The master generates 16 total clock cycles at SCL. The
master outputs a total of 8 bits (MSB first) to the SDA line
at falling edge of the clock. The SDA line is released after
the RWN bit has been transmitted. The slave outputs 8
bits of data (MSB first) at rising edge of the clock. The
master closes the transmission by setting CSEL to 0.
Figure 5 shows the interface timing.
Mode Control
Normal mode allows read-only instruction for all registers
except MODECTRL. Normal mode is the default mode.
Setup mode allows the master to write unrestricted data
into any register except the RXSTAT register. To enter
setup mode, the MODECTRL register (address = H0x0E)
must be set to H0x12. After the MODECTRL register has
been set to H0x12, the next operation is unrestricted.
The setup mode is automatically exited after the next
operation is finished. This sequence must be repeated if
further unrestricted settings are necessary.
Table 9. Digital Communication Word Structure
Table 10. Register Descriptions and Addresses
BIT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Register Address RWN Data that is written or read.
ADDRESS NAME FUNCTION
H0x00 RXCTRL1 Receiver Control Register 1
H0x01 RXCTRL2 Receiver Control Register 2
H0x02 RXSTAT Receiver Status Register
H0x03 SET_CML CML Output Level Setting Register
H0x04 SET_LOS LOS Threshold Assert Level Setting Register
H0x0E MODECTRL General Control Register
H0x12 SET_LOSTIMER LOS Timer Setting Register