Datasheet

______________________________________________________________________________________ 13
MAX3945
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
CML Output Deemphasis
The CML output stage is optimized for differential 100I
transmission lines on a standard FR4 board. The RXDE1
and RXDE0 bits add programmable analog output
deemphasis to compensate for FR4 board losses and
SFP connector losses. Table 5 describes the deempha-
sis control settings.
Programmable CML Output Amplitude
The 8-bit SET_CML register controls the amplitude of the
CML output stage. The maximum programmable output
level depends on the operational mode of the MAX3945.
These output levels (which assume an ideal 100I dif-
ferential load) and their corresponding control bits are
described in Table 6. Table 7 shows the output DAC
resolution dependency.
Figure 2. Functional Diagram
RIN+
SDA
SCL
CSEL
V
CCR
RPMIN
V
CCR
- 1V
BW1
R
IN
R
PULL
R
PULL
R
IN
RIN-
BW0
RATE_SEL
RX_POL
AZ_EN
4G
10G
1
0
MX
LPF
DIGITAL OFFSET CORRECTION
DEEMPHASIS
RXDE1
ROUT+
CAZ
ROUT-
LOS
RXDE0
RX_EN
SQ_EN
V
CCR
R
OUT
R
OUT
OUTPUT
CTRL LOGIC
LOSS OF SIGNAL
LOS_POL LOS2/1_EN
R
PULL
V
EE
3-WIRE
INTERFACE
INTERNAL
REGISTER
CONTROL
LOGIC
7b DAC SET_LOSTIMER
8b DAC SET_CML
6b DAC SET_LOS
V
CCR
MAX3945
1
0