Datasheet
10 _____________________________________________________________________________________
MAX3945
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Pin Configuration
Pin Description
15
16
14
13
5
6
7
V
EE
LOS
8
CAZ
SDA
SCL
RPMIN
1 3
RIN-
4
12 10 9
RIN+
*EP
*THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
+
V
CCR
V
CCR
ROUT-
ROUT+
V
CCR
V
EE
CSEL
2
11
V
CCR
THIN QFN
(3mm × 3mm)
MAX3945
TOP VIEW
PIN NAME FUNCTION
1 CAZ
Offset-Correction Loop Capacitor. A capacitor connected between this pin and the adjacent V
EE
pin sets
the time constant of the offset-correction loop. The offset correction can be disabled through the digital
interface by setting bit AZ_EN = 0 and by connecting this pin to ground.
2, 3 V
EE
Ground for Limiting Amplifier
4 LOS
Loss-of-Signal Output. This output is an open-drain output. LOS is asserted when the level of the input
signal drops below the preset threshold set by SET_LOS[5:0]. LOS is deasserted when the signal level
is above the threshold. The polarity of the LOS output can be inverted by setting LOS_POL = 0. The LOS
circuitry can be disabled by setting LOS1_EN = 0 and LOS2_EN = 0. See Table 8.
5, 8, 13,
16
V
CCR
Power Supply. Provides supply voltage to the limiting amplifier. All pins must be connected to the supply
voltage.
6 ROUT+
Noninverted Output, CML. Back terminated for 50I load.
7 ROUT-
Inverted Output, CML. Back terminated for 50I load.
9 SCL
Serial-Clock Input, TTL/CMOS. This pin has a 75kI internal pulldown.
10 SDA
Serial-Data Bidirectional I/O. TTL/CMOS input and open-drain output. This pin has a 75kI internal pul-
lup, but it requires an external 4.7kI pullup resistor to meet the 3-wire digital timing specification. (Data
line collision protection is implemented.)
11 CSEL
Chip-Select Input, TTL/CMOS. Internally pulled down by a 75kI resistor. CSEL = 1 starts an SPI cycle,
while CSEL = 0 ends the SPI cycle and resets the control state machine.
12 RPMIN High-Impedance Receive Power-Monitor Input. Connect to ground when not used.
14 RIN-
Inverted Data Input, CML, with 50I Termination
15 RIN+
Noninverted Data Input, CML, with 50I Termination
— EP Exposed Pad. Must be soldered to circuit ground.