Datasheet

MAX3885
DC termination between the inverting and noninverting
outputs for proper operation. Do not terminate these
outputs to ground. The synchronization LVDS inputs
(SYNC+, SYNC-) are internally terminated with 100Ω
differential input resistance and, therefore, do not
require external termination.
PECL Inputs
Because of the self-biasing resistor networks, the serial
data and clock PECL inputs (SD+, SD-, SCLK+, SCLK-)
require 53Ω termination to V
CC
- 2V when interfacing
with a PECL source (see Alternative PECL Input
Termination ). This results in an equivalent input resis-
tance of 50Ω.
Applications Information
Alternative PECL Input Termination
Figure 5 shows alternative PECL input-termination
methods. Use Thevenin-equivalent termination when a
V
CC
- 2V termination voltage is not available. When
interfacing with an ECL-output device, the MAX3885’s
internal self-biasing allows easy ECL AC-coupling ter-
mination.
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the MAX3885 high-speed inputs and out-
puts.
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
6 _______________________________________________________________________________________
MAX3885
PECL
INPUTS
Z
O
= 50Ω
Z
O
= 50Ω
133Ω
86.6Ω
133Ω
86.6Ω
+3.3V
MAX3885
PECL
INPUTS
Z
O
= 50Ω
53Ω
Z
O
= 50Ω
-2V
53Ω
-2V
THEVENIN-EQUIVALENT TERMINATION
ECL AC-COUPLING TERMINATION
Figure 5. Alternative PECL Input Termination
SCLK
SD
PCLK
PD0–PD15
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
t
SCLK
= 1 / f
SCLK
t
SU
t
CLK-Q
t
H
Figure 4. Timing Parameters