Datasheet

MAX3885
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
4 _______________________________________________________________________________________
NAME FUNCTION
1, 2, 8, 16, 17,
24, 32, 33, 41,
48, 49, 57, 64
GND Ground
3, 5, 7, 9, 11,
13, 25, 34, 42,
47, 56
V
CC
+3.3V Supply Voltage
PIN
4 SD+
Serial Data Noninverting PECL Input. Data is clocked on the SCLK signal’s positive transi-
tion.
6 SD- Serial Data Inverting PECL Input. Data is clocked on the SCLK signal’s positive transition.
15 SYNC+
Synchronizing Pulse Noninverting LVDS Input. Pulse the SYNC signal high for at least four
SCLK periods to shift the data alignment by dropping one bit.
14 SYNC-
Synchronizing Pulse Inverting LVDS Input. Pulse the SYNC signal high for at least four SCLK
periods to shift the data alignment by dropping one bit.
12 SCLK- Serial Clock Inverting PECL Input
10 SCLK+ Serial Clock Noninverting PECL Input
21, 23, 27, 29,
31, 36, 38, 40,
44, 46, 51, 53,
55, 59, 61, 63
PD0+ to PD15+
Parallel Data Noninverting LVDS Outputs. Data is updated on the negative transition of the
PCLK signal.
20, 22, 26, 28,
30, 35, 37, 39,
43, 45, 50, 52,
54, 58, 60, 62
PD0- to PD15-
Parallel Data Inverting LVDS Outputs. Data is updated on the negative transition of the PCLK
signal.
19 PCLK+ Parallel Clock Noninverting LVDS Output
18 PCLK- Parallel Clock Inverting LVDS Output
Pin Description
SINGLE-ENDED OUTPUT
|
V
OD|
V
PD-
V
OH
V
OS
V
OD, P - P
= V
PD+
- V
PD-
-V
OD
+V
OD
0V
0V (DIFF.)
V
OL
V
PD+
DIFFERENTIAL OUTPUT
V
PD+
- V
PD-
D
PD+
R
L
= 100Ω
V
OD
PD-
V
Figure 1. Driver Output Levels