Datasheet

MAX3873A
Detailed Description
The MAX3873A consists of a fully integrated phase-
locked loop (PLL), input amplifier, and CML output
buffers (Figure 5). The PLL consists of a phase/fre-
quency detector, a loop filter, and a voltage-controlled
oscillator (VCO).
This device is designed to deliver the best combination
of jitter performance and power dissipation by using a
fully differential signal architecture and low-noise
design techniques.
Input Amplifier
The input amplifier provides internal 50Ω line termina-
tions and can accept a differential input amplitude from
50mV
P-P
to 1600mV
P-P
. The structure of the input
amplifier is shown in Figure 9.
Phase Detector
The phase detector incorporated in the MAX3873A pro-
duces a voltage proportional to the phase difference
between the incoming data and the internal clock.
Because of its feedback nature, the PLL drives the
error voltage to zero, aligning the recovered clock to
the center of the incoming data eye for retiming.
Frequency Detector
The digital frequency detector (FD) aids frequency
acquisition during startup conditions. The frequency
difference between the received data and the VCO
clock is derived by sampling the VCO outputs on each
edge of the data input signal. The FD drives the VCO
until the frequency difference is reduced to zero. Once
frequency acquisition is complete, the FD returns to a
neutral state.
Loop Filter and VCO
The phase detector and frequency detector outputs are
summed into the loop filter. An external capacitor, C
F
,
is required to set the PLL damping ratio. See the
Design Procedure section for guidelines on selecting
this capacitor.
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
_______________________________________________________________________________________ 7
PIN NAME FUNCTION
10 SCLKEN
C l ock Outp ut E nab l e, TTL Inp ut. W hen S C LKE N = op en or S C LKE N = hi g h, the cl ock outp uts
( S C LKO± ) ar e enab l ed . When S C LKE N = l ow , the cl ock outp uts ar e d i sab l ed and S C LKO ± = V
CC
.
11 SCLKO- Negative Clock Output, CML. This output can be disabled by setting SCLKEN to low.
12 SCLKO+ Positive Clock Output, CML. This output can be disabled by setting SCLKEN to low.
13 VCC_BUF 3.3V CML Output Buffer Supply Voltage
14 SDO- Negative Data Output, CML
15 SDO+ Positive Data Output, CML
16 LOL Loss-of-Lock Output, TTL (Active Low). The LOL output indicates a PLL lock failure.
17, 20 GND Supply Ground
18 FIL- Negative PLL Loop Filter Connection. Connect a 0.022µF capacitor between FIL+ and FIL-.
19 FIL+ Positive PLL Loop Filter Connection. Connect a 0.022µF capacitor between FIL+ and FIL-.
EP Exposed Pad
Ground. The exposed pad must be soldered to the circuit board ground for proper electrical and
thermal operation.
Pin Description (continued)
Figure 5. Functional Diagram
RATESETFIL-FIL+GNDV
CC
MAX3873A
LOOP
FILTER
FASTRACK
SDO+
SDO-
SDI+
SDI-
SCLKO+
SCLKO-
SCLKEN
MODE
AMP
AMP
AMP
I
Q
PHASE AND
FREQUENCY
DETECTOR
LOL
VCO