Datasheet

MAX3873A
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
4 _______________________________________________________________________________________
Figure 1. Definition of Input Voltage Swing
Figure 2. Definition of Clock-to-Q Delay
(a) AC-COUPLED SINGLE-ENDED INPUT (CML OR PECL)
(b) DC-COUPLED SINGLE-ENDED CML INPUT
25mV
25mV
800mV
800mV
V
CC
+ 0.4V
V
CC
V
CC
- 0.4V
V
CC
V
CC
- 0.4V
V
CC
- 0.8V
SCLKO+
SDO
t
CLK
t
CLK-Q
Figure 4. Definition of LOL Assert Time and Frequency Acquisition Time
INPUT DATA
FREQUENCY ACQUISITION TIME
LOL OUTPUT
LOL ASSERT TIME
Figure 3. Definition of Phase Acquisition Time
SERIAL DATA
1200 BITS OF 1–0 PATTERN
<2μs
FASTRACK
DATA
VCO CLOCK PHASE ALIGNED TO INPUT DATA
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3.0V to 3.6V, C
F
= 0.022µF, T
A
= -40°C to +85°C. Typical values are at V
CC
= 3.3V, 2.488Gbps, T
A
= +25°C, unless otherwise
noted.) (Note 4)
Note 1: At T
A
= -40°C, DC characteristics are guaranteed by design and characterization.
Note 2: CML outputs open.
Note 3: R
L
= 50Ω to V
CC
.
Note 4: AC characteristics are guaranteed by design and characterization.
Note 5: Relative to the falling edge of SCLKO+. See Figure 2.
Note 6: Measured with 2
23
- 1 PRBS.
Note 7: Jitter BW = 12kHz to 20MHz.
Note 8: RATESET = low.
Note 9: RATESET = high.