Datasheet

Applications Information
Select and Enable Controls
The MAX3841 provides two LVCMOS-compatible
select inputs, SEL1 and SEL2. Either data input can be
connected to either or both data outputs. The MAX3841
provides two LVCMOS-compatible enable inputs,
ENO1 and ENO2, so each output can be disabled
independently. The MAX3841 can also be used as a
1:2 driver, 2:1 multiplexer, or a dual 1:1 buffer by using
the LVCMOS control inputs accordingly (see Table 1).
Power-Supply Connections
Each of the input and output power-supply connections
(VCC1IN, VCC2IN, VCC1OUT, VCC2OUT) is indepen-
dent and need not be connected to the same voltage.
The input and output supplies can be connected to
1.8V, 2.5V, or 3.3V, but the core supply (V
CC
) must be
connected to 3.3V for proper operation.
Input and Output Interfaces
The MAX3841 inputs and outputs can be AC-coupled
or DC-coupled according to the application. If an input
or output is not used it should be terminated with 50Ω
to the correct input or output supply voltage. For more
information about interfacing with logic families, refer to
Application Note 291: HFAN-01.0: Introduction to
LVDS, PECL, and CML .
Package and Layout Considerations
The MAX3841 is packaged in a 4mm × 4mm 24-pin thin
QFN with exposed pad. The exposed pad provides
thermal and electrical connectivity to the IC and must
be soldered to a high-frequency ground plane. Use
multiple vias to connect the exposed pad underneath
the package to the PC board ground plane.
Use good layout techniques for the 10Gbps PC board
transmission lines, and configure the layout near the IC to
minimize impedance discontinuities. Power-supply
decoupling capacitors should be located as close as
possible to the IC.
MAX3841
12.5Gbps CML 2 × 2 Crosspoint Switch
_______________________________________________________________________________________ 5
V-
V+
(V+) - (V-)
1200mV
MAX
600mV
MAX
75mV
MIN
150mV
MIN
Figure 2. Definition of Differential Voltage Swing
MAX3841
50Ω50Ω
VCC_IN
IN_+
IN_-
MAX3841
50Ω 50Ω
VCC_OUT
OUT_+
OUT_-
Figure 3. Equivalent CML Input Circuit
Figure 4. Equivalent CML Output Circuit
Table 1. Output Controls
ENO1 ENO2 SEL1 SEL2 OUT1 OUT2
0 0 0 0 IN2 IN1
0 0 0 1 IN2 IN2
0 0 1 0 IN1 IN1
0 0 1 1 IN1 IN2
1 1 X X Disabled Disabled