Datasheet

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MAX3748H
Compact, Low-Power, 155Mbps to 4.25Gbps
Limiting Amplifier
Detailed Description
The MAX3748H limiting amplifier consists of an input
buffer, a multistage amplifier, offset correction circuitry,
an output buffer, power-detection circuitry, and signal-
detect circuitry (see the Functional Diagram).
Input Buffer
The input buffer is shown in Figure 3. It provides 50Ω
termination for each input signal IN+ and IN-. The
MAX3748H can be DC- or AC-coupled to a TIA (TIA out-
put offset degrades receiver performance if DC-coupled).
The MAX3748H CML input buffer is optimized for the
MAX3744 TIA.
Gain Stage
The high-bandwidth gain stage provides approximately
53dB of gain.
Offset Correction Loop
The MAX3748H is susceptible to DC offsets in the signal
path because they have high gain. In communication
systems using NRZ data with a 50% duty cycle, pulse-
width distortion present in the signal or generated in the
transimpedance amplifier appears as an input offset
and is reduced by the offset correction loop. For Gigabit
Ethernet and Fibre Channel applications, no capacitor
is required. For SONET applications, C
AZ
= 0.1μF is
recommended. This capacitor determines the lower 3dB
frequency of the data path.
Figure 1. Power-Supply Current Measurement
Figure 2. LOS Deassert Threshold Set 1dB Below the Minimum
by Receiver Sensitivity (for Selected R
TH
)
Figure 3. CML Input Buffer
V
CC
I
CC
(SUPPLY CURRENT)
I
OUT
(CML
OUTPUT CURRENT)
50Ω
R
TH
50Ω
MAX3748H
1dB
6dB
0V
SIGNAL ON
MAX DEASSERT LEVEL
MIN DEASSERT LEVEL
POWER-DETECT WINDOW
V
IN
TIME
SIGNAL OFF
50Ω 50Ω
75kΩ
IN+
IN-
0.25pF
0.25pF
V
CC
ESD
STRUCTURES