Datasheet

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MAX3748H
Compact, Low-Power, 155Mbps to 4.25Gbps
Limiting Amplifier
Pin Configuration
Pin Description
PIN NAME FUNCTION
1, 4, 12 V
CC
Supply Voltage
2 IN+ Noninverted Input Signal, CML
3 IN- Inverted Input Signal, CML
5 TH
Loss-of-Signal Threshold Pin. Resistor to ground (R
TH
) sets the LOS threshold. Connecting this pin
to V
CC
disables the LOS circuitry and reduces power consumption.
6 DISABLE
Disable Input, CMOS/TTL. The data outputs are held static when this pin is asserted high. The LOS
function remains active when the outputs are disabled. If routed through the DS1858/DS1859 con-
troller IC, no additional ESD protection is required.
7 LOS
Noninverted Loss-of-Signal Output. LOS is asserted high when the signal drops below the assert
threshold set by the TH input. The output is open collector (Figure 5). If routed through the DS1858/
DS1859 controller IC, no additional ESD protection is required.
8, 16 GND Supply Ground
9 OUTPOL
Output Polarity Control Input. Connect to GND for an inversion of polarity through the limiting ampli-
fier and connect to V
CC
for normal operation.
10 OUT- Inverted Data Output, CML
11 OUT+ Noninverted Data Output, CML
13 RSSI
Received-Signal-Strength Indicator. This current output can be used to obtain a ground-referenced
voltage proportional to photodiode current with the MAX3744 by connecting an external resistor
between this pin and GND.
14 CAZ2
Offset Correction Loop Capacitor Connection. A capacitor connected between this pin and CAZ1
extends the time constant of the offset correction loop. Typical value of C
AZ
is 0.1FF. The offset cor-
rection is disabled when the CAZ1 and CAZ2 pins are shorted together.
12
13
14
15
16
V
CC
RSSI
CAZ2
CAZ1
GND
GND
TOP VIEW
LOS
DISABLE
EP
TH
+
11
OUT+
10
OUT-
9
1 2 3 4
8
7
6
5
OUTPOL
V
CC
IN+ IN- V
CC
TQFN
(3mm × 3mm)
MAX3748H