Datasheet

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MAX3748H
Compact, Low-Power, 155Mbps to 4.25Gbps
Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.97V to 3.63V, ambient temperature = -40°C to +85°C, CML output load is 50Ω to V
CC
, C
AZ
= 0.1μF, typical values are
at T
A
= +25°C, V
CC
= 3.3V, unless otherwise specified. The data input transition time is controlled by a 4th-order Bessel filter with
f
-3dB
= 0.75 x 2.667GHz for all data rates of 2.667Gbps and below, and with f
-3dB
= 0.75 x data rate for data rates > 3.2Gbps.)
Note 1: Guaranteed by design and characterization.
Note 2: Between sensitivity and overload, all AC specifications are met.
Note 3: The deterministic jitter caused by this filter is not included in the DJ generation specifications (input).
Note 4: 2
23
- 1 PRBS pattern was substituted by K28.5 pattern to determine the high-speed portion of the deterministic jitter. The
low-speed portion of the DJ (baseline wander) was obtained by measuring the eye width difference between outputs gen-
erated using K28.5 and 2
23
- 1 PRBS patterns.
Note 5: Random jitter was measured without using a filter at the input.
Note 6: The supply current measurement excludes the CML output currents by connecting the CML outputs to a separate V
CC
(see Figure 1).
Note 7: The signal at the input is switched between two amplitudes, Signal_ON and Signal_OFF, as shown in Figure 2.
Note 8: Unless otherwise specified, the pattern for all LOS detect specifications is 2
23
- 1 PRBS.
Note 9: I
CM_INPUT
is the input common mode. I
RSSI
is the current at the RSSI output.
Note 10: Stability is defined as variation over temperature and power supply with respect to the typical gain of the part.