Datasheet

Detailed Description
The limiting amplifiers consist of a multistage amplifier,
offset-correction circuitry, an output buffer, and loss-of-
signal detect circuitry (see the Functional Diagram ).
Input Stage
The input stage is shown in Figure 3. It provides 50Ω ter-
mination to V
REF
for each input signal, IN+ and IN-. The
MAX3747A/MAX3747B should be AC-coupled.
Multistage Amplifier
The high-bandwidth multistage amplifier provides approx-
imately 61dB of gain for the MAX3747A/MAX3747B.
Offset Correction Loop
The MAX3747A/MAX3747B are susceptible to DC offsets
in the signal path because they have high gain. In com-
munication systems using NRZ data with a 50% duty
cycle, pulse-width distortion present in the signal or gener-
ated in the transimpedance amplifier appears as an input
offset and is reduced by the offset correction loop.
The offset correction loop sets a low-frequency cutoff of
3.2kHz.
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
7
Maxim Integrated
Pin Description
NAME
PIN
MAX3747A/
MAX3747B
MICREL
SY8893V
FUNCTION
1 DISABLE EN
Disable Function Pin. The data outputs are held static when this pin is asserted high,
transistor-to-transistor logic (TTL). The data outputs are enabled when this pin is held
low. LOS functions remain active when outputs are disabled. For normal operation
connect to GND.
2 IN+ DIN Noninverted Input Signal
3
IN-
DIN Inverted Input Signal
4V
REF
V
REF
Reference Voltage for LOS Threshold Setting
5 TH LOSLVL
Loss-of-Signal Level Set. A voltage on this pin created by a two-resistor divider sets
the threshold level. Connect one resistor from this pin to V
CC
and another from this pin
to V
REF
(see Figure 5).
6 GND GND Ground
7 LOS LOS
Loss of Signal. Open collector for the MAX3747A; internal 100kΩ pullup to V
CC
for the
MAX3747B. LOS is high when the level of the input signal drops below the preset
threshold set by the TH input. LOS is deasserted low when the signal level is above
the threshold.
8
OUT-
DOUT Inverted Data Output, CML
9 OUT+ DOUT Noninverted Data Output, CML
10 V
CC
V
CC
Positive Power Supply
MAX3747A
MAX3747B
50Ω
50Ω
V
REF
V
CC
ESD
STRUCTURES
Figure 3. Differential Input Stage