Datasheet

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Multiband Analog and

Digital Television Tuner

MAX3543

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Applications Information

RF Inputs and Filters

The MAX3543 features separate low- and high-frequency

inputs. These two inputs are combined to a single input

by an off-chip diplexer circuit as shown in the Typical

Application Circuit. When the desired channel is less

than 345MHz, use RFINL. When the desired input is

greater than 345MHz, use RFINH. Further, when the

desired input is less than 110MHz, an internal lowpass

filter should be enabled to limit high-frequency interfer-

ence incident at the mixer input. The lowpass filter is

enabled by the RFLPF bit in R05[5].

Besides selecting the appropriate input port and setting

RFLPF appropriately, one of three tracking filters must

be chosen based on the desired frequency. Set TFB

(R05[3:2]) to select VHFL, VHFH, or UHF tracking filter

bands. Use VHFL when the desired frequency is less

than 196MHz, use VHFH when the desired frequency

is between 196MHz and 440MHz, or use UHF when the

desired frequency is greater than 440MHz.

RF Gain Control

The MAX3543 is designed to control its own RF gain

based on internally measured signal and blocker levels.

The user can adjust the AGC attack points (takeover

points) by setting WDPA and NDPA in register R0B.

Alternatively, the user can control the RF gain by driving

the RFVGC input pin.

VCO and VCO Divider Selection

The MAX3543 frequency synthesizer includes three

VCOs with 16 sub-bands for each VCO. These VCOs

and sub-bands are selected to best center the VCO

near the operating frequency. This selection process is

performed automatically by the VAS circuitry. The Maxim

driver software seeds the VCO starting band for fastest

selection time.

In addition to VCO selection, a VCO divider value of 32,

16, 8, or 4 must be selected to provide the desired mixer

LO drive frequency. The divider is selected by VDIV in

Reading the ROM Table

The MAX3543 includes 13 ROM registers to store fac-

tory calibration data (see Table 26). Each ROM table

entry must be read using a two-step process. First,

the address of the ROM bits to be read must be pro-

grammed into the ROM ADDR register (R0E[3:0]).

Once the address has been programmed, the data

stored in that address is automatically transferred to the

ROM READBACK register (R10[7:0]). The ROM data at

the specified address can then be read from the ROM

READBACK register and stored in the microprocessor’s

local memory. After all ROM registers have been read

and stored in the microprocessor’s local memory, ROM

ADDR must be programmed to 00 for proper operation.

Table 24. R14: TEST1 Register (Address: 14h)

Table 25. R15: ROM WRITE DATA Register (Address: 15h)

Note: This register is not available to the end user.

BIT NAME

BIT LOCATION

(0 = LSB)

TYPICAL

SETTING

FUNCTION

RESERVED 7:0

0100

0000

Must set to 0100 0000 for proper operation