Datasheet

Block Erase Flash Command
A block of 128 words (256 bytes) can be erased in a
single operation. For the 8KB array, there are 32 such
128 word (256 Byte) blocks. The block to be erased is
selected by the 16-bit address word in the block erase
flash SPI protocol sequence as illustrated in Figure 20.
The erased block is the block that contains the specified
address. The time from CE deassert to CE assert for the
next block erase flash command needs to be approxi-
mately t
ERASE
. Also, the device sets the flash bit in the
Interrupt Status register and asserts the INT device pin
(if enabled) to tell the host microprocessor that the next
block erase flash command can be sent. The host micro-
processor can read the Interrupt Status register after the
INT device pin is asserted instead of waiting for t
ERASE
.
Flash Memory Map
This memory is accessed by the read flash, write flash,
and the block erase flash commands. All flash memory
is erased when the MAX35101 leaves the factory. This
means that each flash location has a value of FFFFh until
written by a user to a different value.
Figure 19. Write Flash Opcode Command Protocol
Figure 20. Block Erase Flash Opcode Command Protocol
WRITE FLASH COMMAND
CE
SCK
DIN
DOUT
O O A A
OPCODE ADDRESS
MSB LSBMSB LSB
A15-
A0 16 BITSD7-D0
HIGH IMPEDANCE
0 1 2 3 4
5 109
876
20 232221
D D
24 25 26 39383736
DATA
MSB LSB
16 BITS
BLOCK ERASE FLASH COMMAND
CE
SCK
DIN
DOUT
O
O A
A
OPCODE ADDRESS
MSB LSBMSB LSB
16 BITS8 BITS
HIGH IMPEDANCE
0 1 2 3 4 5 109876 20 232221
MAX35101 Time-to-Digital Converter with Analog Front-End
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