Datasheet

Flash Opcode Commands
To access the flash memory, the internal low-dropout
voltage regulator that powers the flash circuitry must
be enabled. This can be done two ways: sending the
LDO_Timed command prior to the desired flash access or
sending the LDO_ON command to the MAX35101 prior to
desired flash access. See the LDO_Timed and LDO_ON
command descriptions for details. To manipulate the flash
memory, there are three commands supported by the
device: read flash, write flash, and block erase flash.
Read Flash Command
The read flash command is used to sequentially read
a continuous stream of data from the internal 8KB of
flash using a built-in autoincrement address counter. For
8KB, 13 address bits are needed to indicate the starting
address in memory to begin the read stream. Since the
memory array is organized in X16 fashion, the starting
address must fall on any even number address. The read
stream continues until the CE signal is deasserted. Once
the automatic internal address counter has been incre-
mented to the last memory location in the array, it wraps
around to the bottom of the memory array and the data
for the first memory location of the array is read. Figure 18
illustrates the serial peripheral interface signaling associ-
ated with the read flash command.
Write Flash Command
The flash is written in the MAX35101 in a word-only man-
ner. The architecture allows a single 16-bit word to be
written to the array supporting the maximum access SPI
clock speed of t
SCK
. The location to be programmed must
have previously been erased with the block erase flash
command.
To perform a write flash command, the starting flash
memory address must fall on an even flash memory
address (i.e., the least significant bit of the address (A15–
A0) must be 0). The 16-bit address word and at least one
16-bit word of data must be clocked into the device before
the CE pin is deasserted. If more than 16 bits of data are
clocked into the device during a single CE assertion, only
the last bounded 16-bit data word is written. This is not a
FIFO register. Any fraction of a 16-bit word is ignored, and
the previous whole 16-bit word is written.
Once the 16 bits of data are clocked into the device,
the host microprocessor deasserts the CE device pin
and then waits. The MAX35101 sets the flash bit in the
Interrupt Status register and assert the INT device pin
(if enabled) to tell the host microprocessor that the next
write flash command can be sent to the MAX35101.
The host microprocessor can then read the Interrupt
Status register after the INT device pin is asserted.
Figure 19 illustrates the serial peripheral interface signal-
ing associated with the write flash command.
Figure 18. Read Flash Opcode Command Protocol
CE
SCK
DIN
DOUT
O
O A
A
OPCODE ADDRESS
D
D D
MSB LSBMSB LSB
16 BITS8 BITS
D
D D
D
D D
D
MSBLSBMSB
HIGH IMPEDANCE
HIGH IMPEDANCE
READ FLASH COMMAND
DATA
MAX35101 Time-to-Digital Converter with Analog Front-End
www.maximintegrated.com
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