Datasheet

Table 23. Control Register
WRITE OPCODE
FFh
READ OPCODE
7Fh
FLASH STORED
No
DEFAULT VALUE
0000h
Bit
15 14 13 12 11 10 9 8
Name
X X X X X X AFA CSWA
Bit
7 6 5 4 3 2 1 0
Name
X X X X X X X X
BIT NAME DESCRIPTION
15:10 X
Reserved
9 AFA
Alarm Flag Arm: This bit is set when the RTC’s hours and/or minutes value matched the alarm
settings in the RTC register. This bit is set at the same time as the AF bit in the Interrupt Status
register. After resetting the RTC alarm settings, a 0 must be written to this bit to rearm the RTC
Alarm. This bit can only be written to a 0.
8 CSWA
Case Switch Arm: This bit is set when the CSW pin detects a logic-high, indicating the
MAX35101 has detected a tamper condition. This bit is set at the same time as the CSWI bit in
the Interrupt Status register. Once set, this bit must be written to a 0 to rearm the case switch
detection. The case switch detection must be rearmed before the CSWI interrupt can be set
again. This bit can only be written to a 0.
7:0 X Reserved
MAX35101 Time-to-Digital Converter with Analog Front-End
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