Datasheet

Table 22. Interrupt Status Register (continued)
BIT NAME DESCRIPTION
12 TOF
Time of Flight: Set when the TOF_UP, TOF_DN, or TOF_DIFF command has completed.
During execution of The EVTMG1 or EVTMG2 command, this bit is set and the INT pin asserts
(if enabled) upon completion of each of the cycles of the event dened by the TOF difference
measurements setting if the CONT_INT bit in the Calibration and Control register has been set.
11 TE
Temperature: Set when the temperature command has completed. During execution of The
EVTMG1 or EVTMG3 command, this bit is set and the INT pin asserts (if enabled) upon
completion of each of the cycles of the event dened by the temperature measurements setting if
the CONT_INT bit in the Calibration and Control register has been set.
10 LDO
Internal LDO Stabilized: Set when the internal low-dropout regulator is turned on by either the
LDO_Timed or LDO_ON and has stabilized. Once asserted, a ash command can be sent to the
MAX35101.
9 TOF_EVTMG
Event Timing TOF Completed: Set when either the EVTMG1 or EVTMG2 commands have
completed its last TOF_DIFF measurement cycle. This indicates that the data in the TOF_DIFF,
TOF_DIFF_AVG, AVGUP, and AVGDN Results registers is valid.
8 TEMP_EVTMG
Event Timing Temperature Completed: Set when the EVTMG1 or EVTMG3 commands have
completed its last temperature measurements. This indicates that the data in the T1, T2, T3, T4,
T1_AVG, T2AVG, T3AVG, and T4_AVG Results registers is valid.
7 FLASH
Flash Ready: Set when the ash memory is ready to be accessed. During execution of any
command that requires write access to the ash memory (write ash, transfer conguration
to ash, block erase, initialize), the SPI port is inactive and should not be exercised. The host
microprocessor is interrupted by the assertion of the INT pin (if enabled) once the command has
been completed and the SPI of the MAX35101 is available for access.
6 CAL
Calibrate: Set after completion of the Calibrate command when the command is manually sent
by the host microprocessor. When calibration occurs as a result of the setting of the Cal_Use,
Cal_AUTO and Cal_CFGx bits in the Event Timing 2 register and the MAX35101 is automatically
executing calibration commands as required during execution of any of the EVTMGx commands,
this bit is not set.
5 HALT HALT: Set when the HALT command has completed.
4 CSWI Case Switch: Set when a high logic level is detected on the CSW device pin.
3 INIT Initialize: Set when the Initialize command has completed.
2 POR
Power-On-Reset: Set when the MAX35101 has been successfully powered by application of
V
CC
. Upon application of power, the SPI port becomes inactive until this bit has been set.
1:0 X Reserved
MAX35101 Time-to-Digital Converter with Analog Front-End
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