Datasheet

Table 20. Calibration and Control Register (continued)
Table 21. Real-Time Clock Register
BIT NAME DESCRIPTION
3:0 CAL_PERIOD[3:0]
4MHz Ceramic Oscillator Calibration Period: These bits dene the number of 32.768kHz
oscillator periods to measure for determination of the 4MHz ceramic oscillator period.
32kHz clock cycles = 1+ CAL_PERIOD[3:0]
CAL_PERIOD[3:0] (decimal)
DESCRIPTION
32kHz CLOCK CYCLES
(decimal)
32kHz CLOCK CYCLES
(µs)
0 1 30.5
1 2 61
…. …. ….
14 15 457.7
15 16 488.0
WRITE OPCODE
43h
READ OPCODE
C3h
FLASH-STORED
Yes
FACTORY-STORED FLASH VALUE
0000h
Bit
15 14 13 12 11 10 9 8
Name
X X X X X X X X
Bit
7 6 5 4 3 2 1 0
Name
X 32K_BP 32K_EN EOSC AM1 AM0 WF WD_EN
BIT NAME DESCRIPTION
15:7 X Reserved
6 32K_BP
32kHz Bypass: This bit, when set, allows an external CMOS-level 32.768kHz signal to be applied
to the 32KX1 device pin. The internal 32.768kHz oscillator is bypassed and the external signal is
driven into the MAX35101 core.
5 32K_EN
32kHz Clock Output Enable: This bit enables the 32KOUT device pin to drive a CMOS-level
square wave representation of the 32kHz crystal.
4 EOSC
Enable Oscillator: This active-low bit when set to logic 0 starts the real-time clock oscillator. When
this bit is set to logic 1, the oscillator is stopped.
MAX35101 Time-to-Digital Converter with Analog Front-End
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