Datasheet

Table 19. TOF Measurement Delay Register
Table 20. Calibration and Control Register
WRITE OPCODE
41h
READ OPCODE
C1h
FLASH STORED
Yes
FACTORY-STORED FLASH VALUE
0000h
Bit 15 14 13 12 11 10 9 8
Name DLY15 DLY14 DLY13 DLY12 DLY11 DLY10 DLY9 DLY8
Bit 7 6 5 4 3 2 1 0
Name DLY7 DLY6 DLY5 DLY4 DLY3 DLY2 DLY1 DLY0
BIT NAME DESCRIPTION
15:0 DLY[15:0]
This is hexadecimal value ranging from 0000h to FFFFh (decimal 0 to 65535). It is a multiple of the
4MHz crystal period (250ns). Settings less than 0012h are reserved and should not be used. The
analog comparator driven by the STOP_UP and STOP_DN device pins does not generate a stop
condition until this delay, counted from the internally generated start pulse for the acoustic wave,
has expired. This delay applies to early edge detect wave. Care must be taken to set the TIMOUT
bits in the TOF2 register so that a timeout interrupt does not occur before this delay expires.
WRITE OPCODE
42h
READ OPCODE
C2h
FLASH STORED
Yes
FACTORY-STORED FLASH VALUE
0000h
Bit 15 14 13 12 11 10 9 8
Name X X X X CMP_EN CMP_SEL INT_EN ET_CONT
Bit 7 6 5 4 3 2 1 0
Name CONT_INT CLK_S2 CLK_S1 CLK_S0
CAL_
PERIOD3
CAL_
PERIOD2
CAL_
PERIOD1
CAL_
PERIOD0
BIT NAME DESCRIPTION
15:12 X Reserved
11 CMP_EN
Comparator/UP_DN Output Enable:
1 = CMP_OUT/UP_DN output device pin is enabled.
0 = CMP_OUT/UP_DN output device pin is driven low.
MAX35101 Time-to-Digital Converter with Analog Front-End
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