Datasheet

Table 16. TOF7 Register
Table 15. TOF6 Register (continued)
WRITE OPCODE
3Eh
READ OPCODE
BEh
FLASH STORED
Yes
FACTORY-STORED FLASH VALUE
0000h
Bit 15 14 13 12 11 10 9 8
Name
C_OFFSET
DNR7
C_OFFSET
DNR6
C_OFFSET
DNR5
C_OFFSET
DNR4
C_OFFSET
DNR3
C_OFFSET
DNR2
C_OFFSET
DNR1
C_OFFSET
DNR0
Bit 7 6 5 4 3 2 1 0
Name X
C_OFFSET
DN6
C_OFFSET
DN5
C_OFFSET
DN4
C_OFFSET
DN3
C_OFFSET
DN2
C_OFFSET
DN1
C_OFFSET
DN0
BIT NAME DESCRIPTION
6:0
C_OFFSETUP
[6:0]
Comparator Offset Upstream: These bits dene an initial selected receive comparator offset
voltage for the analog receiver comparator front-end. This comparator offset is used to detect
the early edge wave, t
1
. The actual common-mode voltage is dependent upon and scales with
the voltage present at the V
CC
pins.
When the STOP_POL bit in the TOF1 register is set to zero indicating a rising edge detection of
the zero crossing of the received acoustic wave, then the comparator offset is a positive value.
When the STOP_POL bit in the TOF1 register is set to one indicating a falling edge detection of
the zero crossing of the received acoustic wave, then the comparator offset is a negative value.
The following formulas dene the comparator offset voltage setting
OFFSETUP
CC
OFFSETUP
CC
CC
C
STOP_POL 0 Comparator Offset Voltage V
3072
C
STOP_POL
(1152 + )
(11
1 Comparato
51- )
r Offset Voltage V
3072
V
where 1 LSB
3072
= = ×
= = ×
=
C_OFFSETUP[6:0] OFFSET (LSBs)
00h through 7Fh 0 through 127
MAX35101 Time-to-Digital Converter with Analog Front-End
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