Datasheet

Table 10. TOF1 Register (continued)
BIT NAME DESCRIPTION
15:8 PL[7:0]
Pulse Launcher Size: This is a hex value that denes the number of pulses that will be launched
from the pulse launcher during transmission. The range of this hex value is 00h to FFh. When
PL[7:0] is set to 00h, the Pulse Launcher is disabled. Up to 127 pulses can be launched. When PL7
is set, the pulse count is clamped at 127.
7:4 DPL[3:0]
Pulse Launch Divider: This is a hex value that denes the divider ratio of the internal clock signal
used to drive the Pulse Launch signal. The 4MHz external reference oscillator is used as the source
for the internal clock reference. The internal reference clock is rst divided by 2 to produce a 2MHz
clock. The range of this hex value is 1h to Fh, resulting in a range of division from ÷2 to ÷16 of the
2MHz clock. A value of 0h is not supported and should not be programmed
Pulse Launch Frequency = 2MHz/(1+DPL[3:0])
DPL[3:0] PULSE LAUNCH FREQUENCY
0000b RESERVED
0001b 1MHz
0002b 666kHz
…. ….
1110b 133.33kHz
1111b 125kHz
3 STOP_POL
Stop Polarity: This bit denes the edge sensitivity of the STOP_UP and STOP_DN channel. The
signal received on the STOP_UP and STOP_DN device pins will generate a stop condition for the
internal TDC time count on the rising slope of this signal if this bit is set to 0. The signal received on
the STOP_UP and STOP_DN device pins will generate a stop condition for the internal TDC time
count on the falling slope of this signal if this bit is set to 1.
2 X Reserved
1:0 CT[1:0]
Bias Charge Time: This is the time allotted for charging the external bias network on the STOP
pins to produce common mode biasing for the analog receiver/comparator. It is based upon the
32.768 KHz crystal:
CT1 CT2
DESCRIPTION
32kHz CLOCK CYCLES
(decimal)
TYPICAL TIME (µs)
0 0 2 61
0 1 4 122
1 0 8 244
1 1 16 488
MAX35101 Time-to-Digital Converter with Analog Front-End
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