Datasheet

For proper alarm function, programming of the ALARM
register HOURS bits must match the format (12- or
24-hour modes) used in the Mins_Hrs register.
Watchdog Operation
The MAX35101 also contains a watchdog alarm. The
Watchdog Alarm Counter register is a 16-bit BCD coun-
ter that is programmable in 10ms intervals from 0.01s to
99.99s. A seed value may be written to this register repre-
senting the start value for the countdown. The watchdog
counter begins decrementing when the WD_EN bit in the
RTC register is set.
An immediate read of Watchdog Alarm Counter register
returns the value just written. A read after a wait dura-
tion causes a value seed minus wait to be returned. For
example if the seed value was 28.01s, an immediate read
returns 28.01. A read after a 4s returns 24.01s. The value
read out for any read operation is a snapshot obtained at
the instant of a serial read operation.
A write operation to the Watchdog Alarm Counter register
causes a reload with the newly written seed.
When the watchdog is enabled and a nonzero value is
written into the Watchdog Alarm Counter register, the
Watchdog Alarm Counter register decrements every
1/100s, until it reaches zero. At this point, the WF bit in the
Real-Time Clock register is set and the WDO pin asserts
low for typically 250ms. At the end of the pulse, the WDO
pin becomes high impedance.
The WF flag remains set until cleared by writing WF to
a logic 0 in the Real-Time Clock register. If the WF bit
is cleared while the WDO device pin is being held low,
the WDO device pin is immediately released to its high-
impedance state. Writing a seed value of 0 does not
cause the WF bit to assert.
Tamper Detect Operation
The MAX35101 provides a single input that can be con-
nected to a device case switch and used for tamper
detection. Upon detection of a case switch event the
CSWA in the Control register and the CSWI bit in the
Interrupt Status register is set and the INT device pin is
asserted (if enabled).
Device Interrupt Operations
The MAX35101 is designed to optimize the power effi-
ciency of a flow metering application by allowing the
host microprocessor to remain in a low-power sleep
mode, instead of requiring the microprocessor to keep
track of complex real-time events being performed by
the MAX35101. Upon completion of any command, the
MAX35101 alerts the host microprocessor using the INT
pin. The assertion of the INT pin can be used to awaken
the host microprocessor from its low power mode. Upon
receiving an interrupt on the INT pin, the host micropro-
cessor should read the Interrupt Status Register to deter-
mine which tasks were completed.
Interrupt Status Register
The interrupt status register contains flags for all for all
commands and events that occur within the MAX35101.
These flags are set when the event occurs or at the
completion of the executing command. When the Interrupt
Status Register is read, all asserted bits are cleared. If
another interrupt source has generated an interrupt dur-
ing the read, these new flags assert following the read.
INT Pin
The INT pin asserts when any of the bits in the Interrupt
Status register are set. The INT pin remains asserted until
the Interrupt Status register is read by the user and all bits
in this register are clear. In order for the INT pin to oper-
ate, it must first be enabled by setting the INT_EN bit in
the Calibration and Control register.
Serial Peripheral Interface Operation
Four pins are used for SPI-compatible communications:
DOUT (serial-data out), DIN (serial-data in), CE (chip
enable), and SCK (serial clock). DIN and DOUT are
the serial data input and output pins for the devices,
respectively. The CE input initiates and terminates a data
transfer. SCK synchronizes data movement between the
master (microcontroller) and the slave (MAX35101). The
SCK, which is generated by the microcontroller, is active
only when CE is low and during opcode and data transfer
to any device on the SPI bus. The inactive clock polarity
is logic-low. DIN is latched on the falling edge of SCK.
There is one clock for each bit transferred. Opcode bits
are transferred in groups of eight, MSB first. Data bits are
transferred in groups of sixteen, MSB first.
The serial peripheral interface is used to access the fea-
tures and memory of the MAX35101 using an opcode/
command structure.
MAX35101 Time-to-Digital Converter with Analog Front-End
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