Datasheet

MAX34451 PMBus 16-Channel V/I Monitor and
12-Channel Sequencer/Marginer
www.maximintegrated.com
Maxim Integrated
26
SEQ Pin Operation
The SEQpinisanotheroptionalsignal.Whenthisfunction
is enabled, it allows multiple devices to coordinate event-
based sequencing. With the MFR_CHANNEL_CONFIG
command, any channel can be configured to generate one
of 15 signatures. When the channel crosses its power-
good-on level, it generates the needed SEQ signature if
soenabled.WiththeMFR_SEQ_CONFIGcommand,any
ofthesequencingchannels(PAGES0–11)canbeconfig-
ured to wait for a match on the SEQ pin before asserting
thePSENnoutput.Toensurethatavalid SEQ signal is
received when it should be, the maximum allowable time
isconfiguredintotheMFR_TON_SEQ_MAXcommand.
USER NOTE:
Only one channel should be configured with any one
particular SEQ signature.
If two channels have the
same signature, they might reach their power-good-on
levels at different times and corrupt the SEQ signal.
Allow more than 15ms between consecutive SEQ
signatures.
System Watchdog Timer
The device uses an internal watchdog timer. This timer
is internally reset every 5ms. In the event the device is
locked up, and the watchdog reset does not occur after
210ms,thedeviceisautomaticallyreset.Afterthereset
occurs, the device reloads all configuration values that
were stored to flash and begins normal operation. After
thereset,thedevicealsodoesthefollowing:
1) SetstheMFRbitinSTATUS_WORD.
2) Sets the WATCHDOG_INT bit in STATUS_MFR_
SPECIFIC(forPAGE255).
3) NotifiesthehostthroughALERT assertion (if enabled
inMFR_MODE).
CRC Memory Check
Uponreset,thedevicerunsaninternalalgorithmtocheck
the integrity of the key internal nonvolatile memory. If
theCRCcheckfails,thedevicedoesnotpowerupand
remains in a null state with all pins high impedance but
asserts the FAULT0 output.
Figure 4. Multiple MAX34451 Hardware Connections
SCL/SDA (UNIQUE ADDRESS)
CONTROL0
MAX34451
CONTROL1
HARDWARE
CONTROL
PMBus
CONTROL
FAULT0
FAULT1 (OPTIONAL)
FAULT2 (OPTIONAL)
SEQ (OPTIONAL)
SCL/SDA (UNIQUE ADDRESS)
CONTROL0
MAX34451
CONTROL1
FAULT0
FAULT1 (OPTIONAL)
FAULT2 (OPTIONAL)
SEQ (OPTIONAL)
SCL/SDA (UNIQUE ADDRESS)
CONTROL0
MAX34451
CONTROL1
FAULT0
FAULT1 (OPTIONAL)
FAULT2 (OPTIONAL)
SEQ (OPTIONAL)