Datasheet

����������������������������������������������������������������� Maxim Integrated Products 6
MAX34406
Quad Current-Sense Amplifier
with Overcurrent Threshold Comparators
Pin Description (continued)
PIN NAME FUNCTION
14 IN3- External Sense Resistor Load-Side Connection for Amplifier 3
15 OUT3 Output Voltage from Amplifier 3 Proportional to V
SENSE
. This output is clamped at 6V.
16 OUT4 Output Voltage from Amplifier 4 Proportional to V
SENSE
. This output is clamped at 6V.
17 IN4- External Sense Resistor Load-Side Connection for Amplifier 4
18 IN4+
External Sense Resistor Power-Side Connection for Amplifier 4. Bias at this pin also provides the supply
voltage for amplifier 4. This pin can be left open circuit if not needed.
19 V
DD
Supply Voltage for Reference, Comparators, and Logic. A +2.7V to +5.5V supply. This pin should be
decoupled to GND with a 100nF ceramic capacitor.
20 ENA
SHTDN Enable Input. CMOS digital input. Connect to GND to clear the latch and unconditionally
deassert (force low) the SHTDN output. Connect to V
DD
to enable normal latch operation of the SHTDN
output. ENA should be toggled low once V
DD
reaches nominal operating voltage.
21 SHTDN
Shutdown Output. Open-drain output. This output transitions to high impedance when any of the four
overcurrent comparator outputs (OC1 to OC4) are asserted (high impedance) as long as the ENA pin is
high. Toggling the ENA pin allows SHTDN to reset to logic-low.
22 CDLY
Shutdown Delay Capacitor. A capacitor (C
CDLY
) from this pin to GND delays the transition of the
SHTDN pin. The delay time can be calculated by the following formula: t
DLY
= C
CDLY
x (V
DD
/10FA). The
capacitor connected to CDLY is discharged when ENA is low and upon V
DD
being applied (i.e., at power-
on reset), and also any time all OCx outputs are low (i.e., inactive). If the shutdown delay is not required,
this pin can be left unconnected.
24 GND Ground Reference
— EP Exposed Pad. Connect to ground or leave unconnected.