Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsMAX3421EETJ+

MAX3421E

USB Peripheral/Host Controller

with SPI Interface

Maxim Integrated

Note 1b: In peripheral mode, the MAX3421E performs identically to the MAX3420E with the following enhancements:

1) R16 adds the PULSEWID0 and PULSEWID1 bits to control the INT pulse width in edge interrupt mode

(see Figure 12.) These bits default to the MAX3420E setting of 10.6µs.

2) R21 adds four more GPIO bits.

3) R22 and R23 add general-purpose input pins to the interrupt system. R24 controls the edge polarity.

4) R27 controls the peripheral/host mode and the SEPIRQ bit.

5) When [GPXB:GPXA] = [1:0] and the bit SEPIRQ = 1 (R27 bit 4), the GPX output replaces the BUSACT

signal with a second IRQ pin dedicated to the GPIN pin interrupts.

Table 2. MAX3421E Register Map in Host Mode (HOST = 1) (Note 2)

R EG NAME b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 a c c

R0 — 0 0 0 0 0 0 0 0 —

RCVFIFO

b 7b 6b 5b 4b 3b 2b 1b 0RS C

SNDFIFO

b 7b 6b 5b 4b 3b 2b 1b 0RS C

R3 — 0 0 0 0 0 0 0 0 —

SUDFIFO

b 7b 6b 5b 4b 3b 2b 1b 0RS C

R5 — 0 0 0 0 0 0 0 0 —

RCVBC

0BC 6BC 5BC 4BC 3BC 2BC 1BC 0RS C

SNDBC

0BC 6BC 5BC 4BC 3BC 2BC 1BC 0RS C

—

00000 0 0 0—

—

00000 0 0 0—

R10

—

00000 0 0 0—

R11

—

00000 0 0 0—

R12

—

00000 0 0 0—

R13

USBIRQ

0V BU S IRQ N OV BU S IRQ 0 0 0 0 OS C OKIRQ RC

R14

USBIEN

0V BU S IE N OV BU S IE 0 0 0 0 OS C OKIE RS C

R15

USBCTL

00C H IP RE S P WRD OWN 0 0 0 0 RS C

R16

CPUCTL

P U LS E WID 1P U LS E WID 00 0 0 0 0 IE RS C

R17

PINCTL

E P 3IN AK E P 2IN AK E P 0IN AK FD U P S P IIN TLE V E LP OS IN TGP X BGP X ARS C

R18

REVISION

00010 0 1 1R

R19

—

00000 0 0 0—

R20

IOPINS1

GP IN 3GP IN 2GP IN 1GP IN 0GP O U T3 GP O U T2 GP O U T1 GP O U T0 RS C

R21

IOPINS2

GP IN 7GP IN 6GP IN 5GP IN 4GP O U T7 GP O U T6 GP O U T5 GP O U T4 RS C

R22

GPINIRQ

GP IN IRQ7 GP IN IRQ6 GP IN IRQ5 GP IN IRQ4 GP IN IRQ3 GP IN IRQ2 GP IN IRQ1 GP IN IRQ0 RC

R23

GPINIEN

GP IN IE N 7GP IN IE N 6GP IN IE N 5GP IN IE N 4GP IN IE N 3GP IN IE N 2GP IN IE N 1GP IN IE N 0RS C

R24

GPINPOL

GP IN P OL7 GP IN P OL6 GP IN P OL5 GP IN P OL4 GP IN P OL3 GP IN P OL2 GP IN P OL1 GP IN P OL0 RS C

R25

HIRQ

H X FRD N IRQ FRAM E IRQ C ON N IRQ S U S D N IRQ S N D BAV IRQ RC V D AV IRQ RS M RE QIRQ BU S E V E N TIRQ RC

R26

HIEN

H X FRD N IE FRAM E IE C ON N IE S U S D N IE S N D BAV IE RC V D AV IE RS M RE QIE BU S E V E N TIE RS C

R27

MODE

D P P U LLD N D M P U LLD N D E LAY IS OS E P IRQ S OFKAE N AB H U BP RE S P E E D H OS T = 1RS C

R28

PERADDR

0b 6b 5b 4b 3b 2b 1b 0RS C

R29

HCTL

S N D TOG1 S N D TOG0 RC V TOG1 RC V TOG0 S IG RS M BU S S AM P LE FRM RS TBU S RS TLS

R30

HXFR

H S IS O OU TN IN S E TU P E P 3E P 2E P 1E P 0LS

R31

HRSL

JS TATU S KS TATU S S N D TOGRD RC V TOGRD H RS LT3 H RS LT2 H RS LT1 H RS LT0 R

Table 1. MAX3421E Register Map in Peripheral Mode (HOST = 0) (Notes 1a, 1b) (continued)