Datasheet
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
8
Maxim Integrated
Table 1. MAX3421E Register Map in Peripheral Mode (HOST = 0) (Notes 1a, 1b)
R EG NAME b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 a c c
R0 EP0 F IF O b 7b 6b 5b 4b 3b 2b 1b 0RS C
R1 EP1 O U T F IF O b 7b 6b 5b 4b 3b 2b 1b 0RS C
R2 EP2 IN F IF O b 7b 6b 5b 4b 3b 2b 1b 0RS C
R3 EP3 IN F IF O b 7b 6b 5b 4b 3b 2b 1b 0RS C
R4 SU D F IF O b 7b 6b 5b 4b 3b 2b 1b 0RS C
R5 EP0 B C 0b 6b 5b 4b 3b 2b 1b 0RS C
R6 EP1 O U T B C 0b 6b 5b 4b 3b 2b 1b 0RS C
R7 EP2 IN B C 0b 6b 5b 4b 3b 2b 1b 0RS C
R8 EP3 IN B C 0b 6b 5b 4b 3b 2b 1b 0RS C
R9 EPST A L L S 0AC KS TAT S TLS TAT S TLE P 3IN S TLE P 2IN S TLE P 1OU TS TLE P 0OU TS TLE P 0IN RS C
R10 C L R T O G S E P 3D IS AB E P 2D IS AB E P 1D IS AB C TG E P 3IN C TG E P 2IN C TG E P 1OU T0 0RS C
R11 EPI R Q 00S U D AV IRQ IN 3BAV IRQ IN 2BAV IRQ OU T1D AV IRQ OU T0D AV IRQ IN 0BAV IRQ RC
R12 EPI EN 00S U D AV IE IN 3BAV IE IN 2BAV IE OU T1D AV IE OU T0D AV IE IN 0BAV IE RS C
R13 U SB IR Q U RE S D N IRQ V BU S IRQ N OV BU S IRQ S U S P IRQ U RE S IRQ BU S AC TIRQ RWU D N IRQ OS C OKIRQ RC
R14 U SB IEN U RE S D N IE V BU S IE N OV BU S IE S U S P IE U RE S IE BU S AC TIE RWU D N IE OS C OKIE RS C
R15 U SB C T L H OS C S TE N V BG ATE C H IP RE S P WRD OWN C ON N E C TS IG RWU 0 0 RS C
R16 C PU C T L P U LS E WID 1P U LS E WID 00 0 0 0 0 IE RS C
R17 PIN C T L E P 3IN AK E P 2IN AK E P 0IN AK FD U P S P IIN TLE V E LP OS IN TGP X BGP X ARS C
R18 R EVISIO N 00 010 0 1 1R
R19 F N A D D R 0b 6b 5b 4b 3b 2b 1b 0R
R20 IO PIN S1 GP IN 3GP IN 2GP IN 1GP IN 0GP O U T3 GP O U T2 GP O U T1 GP O U T0 RS C
R21
IOPINS2
GP IN 7GP IN 6GP IN 5GP IN 4GP O U T7 GP O U T6 GP O U T5 GP O U T4 RS C
R22
GPINIRQ
GP IN IRQ7 GP IN IRQ6 GP IN IRQ5 GP IN IRQ4 GP IN IRQ3 GP IN IRQ2 GP IN IRQ1 GP IN IRQ0 RS C
R23
GPINIEN
GP IN IE N 7GP IN IE N 6GP IN IE N 5GP IN IE N 4GP IN IE N 3GP IN IE N 2GP IN IE N 1GP IN IE N 0RS C
R24
GPINPOL
GP IN P OL7 GP IN P OL6 GP IN P OL5 GP IN P OL4 GP IN P OL3 GP IN P OL2 GP IN P OL1 GP IN P OL0 RS C
R25
—
00 000 0 0 0—
R26
—
00 000 0 0 0—
R27
MODE
00 0S E P IRQ 0 0 0 H OS T = 0RS C
R28
—
00 000 0 0 0—
R29
—
00 000 0 0 0—
R30
—
00 000 0 0 0—
R31
—
00 000 0 0 0—
Note 1a: The acc (access) column indicates how the SPI master can access the register.
R = read, RC = read or clear, RSC = read, set, or clear.
Writing to an R register (read only) has no effect.
Writing a 1 to an RC bit (read or clear) clears the bit.
Writing a zero to an RC bit has no effect.