Datasheet

MAX3421E
USB Peripheral/Host Controller
with SPI Interface
6
Maxim Integrated
Pin Description (continued)
PIN NAME
INPUT/
OUTPUT
FUNCTION
21 D+
Input/
Output
USB D+ Signal. Connect D+ to a USB connector through a 33Ω ±1% series resistor. A
switchable 1.5kΩ D+ pullup resistor and 15kΩ D+ pulldown resistor is internal to the device.
22 VBCOMP Input
V
BUS
Comparator Input. VBCOMP is internally connected to a voltage comparator to allow the
SPI master to detect (through an interrupt or checking a register bit) the presence or loss of
power on V
BUS
. Bypass VBCOMP to ground with a 1.0µF ceramic capacitor. VBCOMP is pulled
down to ground with R
IN
(see Electrical Characteristics).
23 V
CC
Input
U S B Tr anscei ver and Log i c C or e P ow er - S up p l y Inp ut. C onnect V
C C
to a p osi ti ve 3.3V p ow er
sup p l y. Byp ass V
C C
to g r ound w i th a 1.0µF cer am i c cap aci tor as cl ose to the V
C C
p i n as p ossi b l e.
24 XI Input
Crystal Oscillator Input. Connect XI to one side of a parallel resonant 12MHz ±0.25% crystal
and a load capacitor to GND. XI can also be driven by an external clock referenced to V
CC
.
25 XO Output
C r ystal Osci l l ator O utp ut. C onnect X O to the other si d e of a p ar al l el r esonant 12M H z ± 0.25% cr ystal
and a l oad cap aci tor to GN D . Leave X O unconnected i f X I i s d r i ven w i th an exter nal sour ce.
26 GPIN0
27 GPIN1
28 GPIN2
29 GPIN3
30 GPIN4
31 GPIN5
32 GPIN6
Input
General-Purpose Inputs. GPIN7–GPIN0 are connected to V
L
with internal pullup resistors.
GPIN7–GPIN0 logic levels are referenced to the voltage on V
L
.
— EP Input
E xp osed P ad , C onnected to G r ound . C onnect E P to G N D or l eave unconnected . E P i s l ocated on
the b ottom of the TQ FN p ackag e. The TQFP p ackag e d oes not have an exp osed p ad .