Datasheet

MAX3421E
USB Peripheral/Host Controller
with SPI Interface
5
Maxim Integrated
Pin Description
PIN NAME
INPUT/
OUTPUT
FUNCTION
1 GPIN7 Input
General-Purpose Input. GPIN7–GPIN0 are connected to V
L
with internal pullup resistors.
GPIN7–GPIN0 logic levels are referenced to the voltage on V
L
.
2V
L
Input
Level-Translator Voltage Input. Connect V
L
to the system’s 1.4V to 3.6V logic-level power
supply. Bypass V
L
to ground with a 0.1µF capacitor as close to V
L
as possible.
3, 19 GND Input Ground
4 GPOUT0
5 GPOUT1
6 GPOUT2
7 GPOUT3
8 GPOUT4
9 GPOUT5
10 GPOUT6
11 GPOUT7
Output
General-Purpose Push-Pull Outputs. GPOUT7–GPOUT0 logic levels are referenced to the
voltage on V
L
.
12 RES Input
Device Reset. Drive RES low to clear all of the internal registers except for PINCTL (R17),
USBCTL (R15), and SPI logic. The logic level is referenced to the voltage on V
L
. (See the
Device Reset section for a description of resets available on the MAX3421E.) Note: The
MAX3421E is internally reset if either V
C C
or V
L
is not present. The register file is not accessible
under these conditions.
13 SCLK Input
S P I S er i al - C l ock Inp ut. An exter nal S P I m aster sup p l i es S C LK w i th fr eq uenci es up to 26M H z. The
l og i c l evel i s r efer enced to the vol tag e on V
L
. D ata i s cl ocked i nto the S P I sl ave i nter face on the
r i si ng ed g e of S C LK. D ata i s cl ocked out of the S P I sl ave i nter face on the fal l i ng ed g e of S C LK.
14 SS Input
SPI Slave Select Input. The SS logic level is referenced to the voltage on V
L
. When SS is driven
high, the SPI slave interface is not selected, the MISO pin is high impedance, and SCLK
transitions are ignored. An SPI transfer begins with a high-to-low SS transition and ends with a
low-to-high SS transition.
15 MISO Output
SPI Serial-Data Output (Master-In Slave-Out). MISO is a push-pull output. MISO is tri-stated in
half-duplex mode or when SS = 1. The MISO logic level is referenced to the voltage on V
L
.
16 MOSI
Input or
Input/
Output
SPI Serial-Data Input (Master-Out Slave-In). The logic level on MOSI is referenced to the
voltage on V
L
. MOSI can also be configured as a bidirectional MOSI/MISO input and output.
(See Figure 15.)
17 GPX Output
G ener al - P ur p ose M ul ti p l exed P ush- P ul l O utp ut. The i nter nal M AX 3421E si g nal that ap p ear s on
G P X i s p r og r am m ab l e b y w r i ti ng to the G P X B and G P X A b i ts of the P IN C TL ( R17) r eg i ster and the
S E P IRQ b i t of the M O D E ( R27) r eg i ster . GP X i nd i cates one of fi ve si g nal s ( see the G P X secti on) .
18 INT Output
Interrupt Output. In edge mode, the logic level on INT is referenced to the voltage on V
L
and is
a push-pull output with programmable polarity. In level mode, INT is open-drain and active low.
Set the IE bit in the CPUCTL (R16) register to enable INT.
20 D-
Input/
Output
USB D- Signal. Connect D- to a USB connector through a 33Ω ±1% series resistor. A
switchable 15kΩ D- pulldown resistor is internal to the device.