Datasheet
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
24
Maxim Integrated
C
LOAD
: 18pF (max)
C
O
: 7pF (max)
Drive level: 200µW
Series resonance resistance: 60Ω (max)
Note: Series resonance resistance is the resistance
observed when the resonator is in the series resonant
condition. This is a parameter often stated by quartz crys-
tal vendors and is called R1. When a resonator is used in
the parallel resonant mode with an external load capaci-
tance, as is the case with the MAX3421E oscillator circuit,
the effective resistance is sometimes stated. This effec-
tive resistance at the loaded frequency of oscillation is:
R1 x ( 1 + (C
O
/ C
LOAD
))
2
For typical C
O
and C
LOAD
values, the effective resis-
tance can be greater than R1 by a factor of 2.
MAX3421E in a Bus-Powered Peripheral
Application
Figure 19 depicts the MAX3421E in a peripheral device
that is powered by V
BUS
. This configuration is advanta-
geous because it requires no external power supply.
V
BUS
is specified from 4.75V to 5.25V, requiring a 3.3V
regulator to power the MAX3421E. This diagram
assumes that the microprocessor is powered by 3.3V
as well, so the V
L
pin (logic-level reference voltage) is
connected to V
CC
. Therefore, the GPIOs (general-pur-
pose inputs/outputs) are referenced to 3.3V.
USB is a hot-plug system (V
BUS
is powered when the
device is plugged in), so it is good design practice to
use a power-on reset circuit to provide a clean reset to
the system when the device is plugged in. The
MAX6349TL serves as an excellent USB regulator,
since it has very low quiescent current and a POR cir-
cuit built in.
Because this design is bus powered, it is not necessary
to test for the presence of V
BUS
. In this case, the bus
voltage-detection input, VBCOMP, makes an excellent
general-purpose input. The VBCOMP input has two inter-
rupts associated with it, VBUSIRQ and NOVBUSIRQ.
These interrupts can detect both edges of any transitions
on the VBCOMP input.
The configuration in Figure 19 shows the SPI interface
using the maximum number of SPI interface pins. The
data pins, MOSI and MISO, are separate, and the
MAX3421E supplies an interrupt signal through the INT
output pin to the µP to notify the µP when its attention
is required.
MAX3421E
V
CC
V
L
XI
XO
INT
MOSI
MISO
SCLK
RES
D+
D-
D+
D-
VBCOMP
SS
0.1μF
GND
V
BUS
33Ω
33Ω
1.0μF
CERAMIC
C
XI
C
XO
12MHz
3.3V
REGULATOR
MAX6349TL
μP
88
USB "B"
CONNECTOR
GND GPIN GPOUT
4.7μF
GPIO
GPI
Figure 19. MAX3421E in a Bus-Powered Peripheral Application