Datasheet

MAX3421E
USB Peripheral/Host Controller
with SPI Interface
14
Maxim Integrated
Test Circuits and Timing Diagrams
Figure 8. Rise and Fall Times
V
OL
V
OH
t
RISE
t
FALL
90%
10%
Figure 9. Load for D+/D- AC Measurements
MAX3421E
D+ OR D-
TEST
POINT
33Ω
15kΩ
C
L
SCLK
SS
MOSI
MISO
t
DS
t
DH
t
CL
t
DO
t
CH
t
T
8
1
2
9
10 16
t
L
t
CSS
t
CSW
t
CP
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 11. SPI Bus Timing Diagram (Half-Duplex Mode, SPI Mode (0,0))
SCLK
MOSI
MISO
NOTES:
1) DURING THE FIRST 8 CLOCKS CYCLES, THE MOSI PIN IS HIGH IMPEDANCE AND THE SPI MASTER DRIVES DATA ONTO THE MOSI PIN. SETUP AND HOLD TIMES ARE THE SAME AS
FOR FULL-DUPLEX MODE.
2) FOR SPI WRITE CYCLES, THE MOSI PIN CONTINUES TO BE HIGH IMPEDANCE AND THE EXTERNAL MASTER CONTINUES TO DRIVE MOSI.
3) FOR SPI READ CYCLES, AFTER THE 8TH CLOCK-FALLING EDGE, THE MAX3421E STARTS DRIVING THE MOSI PIN AFTER TIME t
ON
. THE EXTERNAL MASTER MUST TURN
OFF ITS DRIVER TO THE MOSI PIN BEFORE t
ON
TO AVOID CONTENTION. PROPAGATION DELAYS ARE THE SAME AS FOR THE MOSI PIN IN FULL-DUPLEX MODE.
t
DS
t
DH
t
CL
t
CH
t
DI
t
OFF
t
T
SS
HI-Z
8
1
2
9
10 16
t
L
t
CSW
t
ON
t
CP
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 10. SPI Bus Timing Diagram (Full-Duplex Mode, SPI Mode (0,0))