Datasheet
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
10
Maxim Integrated
MAX3421E
TQFP
(5mm x 5mm)
TOP VIEW
29
30
28
27
12
11
13
V
L
GPOUT0
GPOUT1
GPOUT2
GPOUT3
14
GPIN7
V
CC
D+
D-
XI
GND
INT
12
GPIN2
4567
2324 22 20 19 18
GPIN3
GPIN4
SS
SCLK
RES
GPOUT7
GND
VBCOMP
3
21
31
10
GPIN5
GPOUT6
32
9
GPIN6
GPOUT5
GPIN1
26
15
MISO
GPIN0
25
16
MOSI
GPOUT4
GPX
8
17
XO
+
Pin Configurations
Note 2: The acc (access) column indicates how the SPI master can access the register.
R = read; RC = read or clear; RSC = read, set, or clear; LS = load-sensitive.
Writing to an R register (read only) has no effect.
Writing a 1 to an RC bit (read or clear) clears the bit.
Writing a zero to an RC bit has no effect.
Writing to an LS register initiates a host operation based on the contents of the register.
MAX3421E
TQFN
(5mm x 5mm)
TOP VIEW OF BOTTOM LEADS
29
30
28
27
12
11
13
V
L
GPOUT0
GPOUT1
GPOUT2
GPOUT3
14
GPIN7
V
CC
D+
D-
XI
GND
INT
12
GPIN2
4567
2324 22 20 19 18
GPIN3
GPIN4
SS
SCLK
RES
GPOUT7
GND
VBCOMP
3
21
31
10
GPIN5
GPOUT6
32
9
GPIN6
GPOUT5
GPIN1
26
15
MISO
GPIN0
25
16
MOSI
GPOUT4
GPX
8
17
XO
+
*EXPOSED PAD CONNECTED TO GROUND
*EP
Table 2. MAX3421E Register Map in Host Mode (HOST = 1) (Note 2) (continued)