Datasheet

capacitive isolation between I/O lines. When one or
both I/O lines are at a logic-low level, the gate-control
logic turns the pass-FET on. When the pass-FET is
active, I/O V
L
_ and I/O V
CC
_ are connected, allowing
the logic-low signal to be expressed simultaneously on
both I/O lines.
The MAX3394E/MAX3395E/MAX3396E have internal
10kΩ (typ) pullup resistors from I/O V
L
_ and I/O V
CC
_
to the respective supply voltages, allowing operation
with open-drain drivers. Internal slew-rate enhancement
circuitry accelerates logic-state transitions, maintaining
a fast data rate with a higher bus load capacitance.
Additionally, the 10mA current sink drivers permit the
use of smaller external pullup resistors.
Internal Slew-Rate Enhancement
Internal slew-rate enhancement circuitry accelerates
logic-state changes by turning on MOSFETs M
P1
and
M
P2
during low-to-high logic transitions, and MOSFETs
M
N3
and M
N4
during high-to-low logic transitions (see
the
Functional Diagram ). During logic-state changes,
speed-up MOSFETS are triggered by I/O line voltage
thresholds. MOSFETS M
N3
and M
N4
sink 10mA during
high-to-low logic transitions. M
P1
and M
P2
source 15mA
during low-to-high logic transitions. Slew-rate enhance-
ment allows a fast data rate despite large capacitive bus
loads, and permits larger external pullup resistors.
MAX3394E/MAX3395E/MAX3396E
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
_______________________________________________________________________________________ 9
MAX3394E
MAX3395E
MAX3396E
t
FVL
t
RVL
t
I/OVCC-VL
I/O V
L_
I/O V
CC_
V
L
V
L
V
CC
10%
10%
90%
90%
50%
50%
50%
50%
V
CC
C
IOVL
t
I/OVCC-VL
I/O V
CC
V
L
V
CC
EN
50Ω
I/O V
L
Figure 3. Push-Pull Driving I/O V
CC_
Test Circuit and Timing
MAX3394E
MAX3395E
MAX3396E
t
I/OVCC-VL
I/O V
L_
I/O V
CC_
V
L
V
L
V
CC
10%
10%
90%
90%
50%
50%
50%
50%
V
CC
C
IOVL
t
I/OVCC-VL
I/O V
L
V
L
V
CC
EN
t
FVL
t
RVL
V
GATE
Figure 4. Open-Drain Driving I/O V
CC_
Test Circuit and Timing