Datasheet

MAX3353E
USB On-the-Go Charge Pump with Switchable
Pullup/Pulldown Resistors
_______________________________________________________________________________________ 5
TIMING CHARACTERISTICS (continued)
(V
CC
= +2.6V to +5.5V, V
L
= +1.65V to V
CC
, V
TRM
= +3V to +3.6V, C
FLYING
= 0.1µF, V
CC
decoupled with 1µF capacitor to ground.
V
TRM
and V
L
decoupled with 0.1µF capacitor to ground. C
VBUS
= 1µF (min), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical val-
ues are at T
A
= +25°C, V
CC
= +4V, V
L
= +1.8V, V
TRM
= +3.3V.) (Notes 3, 4)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
INT Out Fall Time C
LOAD
= 50pF 20 ns
ID_OUT Rise Time C
LOAD
= 50pF 30 ns
ID_OUT Fall Time C
LOAD
= 50pF 10 ns
Time to Exit Shutdown 500 µs
Time to Enter Shutdown 1000 µs
I
2
C/SMBUS-COMPATIBLE TIMING SPECIFICATIONS
(V
CC
= +2.6V to +5.5V, V
L
= +1.65V to V
CC
, V
TRM
= +3V to +3.6V, C
FLYING
= 0.1µF, V
CC
decoupled with 1µF capacitor to ground.
V
TRM
and V
L
decoupled with 0.1µF capacitor to ground. C
VBUS
= 1µF (min). T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical val-
ues are at V
CC
= +4V, V
L
= +1.8V, V
TRM
= +3.3V, and T
A
= +25°C.) (Notes 3, 4)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Serial Clock Frequency f
SCL
DC 400 kHz
Bus Free Time Between Stop and
Start Conditions
t
BUF
1.3 µs
Start Condition Hold Time t
HD:STA
0.6 µs
Stop Condition Setup Time t
SU:STO
0.6 µs
Clock Low Period t
LOW
1.3 µs
Clock High Period t
HIGH
0.6 µs
Data Setup Time t
SU:DAT
100 ns
Data Hold Time t
HD:DAT
(Note 7) 0 0.9 µs
Maximum Receive SCL/SDA Rise
Time
t
R
(Note 8) 300 ns
Minimum Receive SCL/SDA Rise
Time
t
R
(Note 8) 20 + 0.1C
B
ns
Maximum Receive SCL/SDA Fall
Time
t
F
(Note 8) 300 ns
Minimum Receive SCL/SDA Fall
Time
t
F
(Note 8) 20 + 0.1C
B
ns
t
F
C
B
= 400pF, I
SDA
= 3mA, V
L
≥ 2.5V 20 + 0.1C
B
250
Transmit SDA Fall Time (Note 4)
t
F
C
B
= 50pF, I
SDA
= 3mA, V
L
< 2.5 20 + 0.1C
B
250
ns
Pulse Width of Suppressed Spike t
SP
(Note 9) 50 ns
Note 3: All currents into the device are negative; currents out of the device are positive. All voltages are referenced to device
ground unless otherwise specified.
Note 4: Parameters are 100% production tested at +25°C, limits over temperature are guaranteed by design.
Note 5: The V
BUS
current source and current gate time vary together with process and temperature such that the resulting V
BUS
pulse is guaranteed to drive a <13µF load to a voltage >2.0V, and to drive a >96µF load to a volatge <2.2V. See the SRP
V
BUS
Pulsing section for an explanation of this self-timed pulse.
Note 6: Guaranteed by design, not production tested.
Note 7: A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL’s falling
edge.
Note 8: C
B
is total capacitance of one bus line in pF. Tested with C
B
= 400pF.
Note 9: Input filters on SDA, SCL, and ADD suppress noise spikes less than 50ns.