Datasheet

MAX3301E/MAX3302E
USB On-the-Go Transceivers and Charge Pumps
6 _______________________________________________________________________________________
I
2
C-/SMBus™-COMPATIBLE TIMING SPECIFICATIONS
(V
CC
= +3V to +4.5V, V
L
= +1.65V to +3.6V, C
FLYING
= 100nF, C
VBUS
= 1µF, ESR
CVBUS
= 0.1Ω (max), T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at V
CC
= +3.7V, V
L
= +2.5V, T
A
= +25°C.) (Note 2)
PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS
Serial Clock Frequency f
SCL
400 kHz
Bus-Free Time Between Stop and
Start Conditions
t
BUF
1.3 µs
Start-Condition Hold Time t
HD_STA
0.6 µs
Stop-Condition Setup Time t
SU_STO
0.6 µs
Clock Low Period t
LOW
1.3 µs
Clock High Period t
HIGH
0.6 µs
Data Setup Time t
SU_DAT
100 ns
Data Hold Time t
HD_DAT
(Note 4) 0.9 µs
Rise Time of SDA and SCL t
R
(Note 5)
20 +
0.1 x
C
B
300 ns
Fall Time of SDA and SCL t
F
Measured from 0.3 x V
L
to 0.7 x V
L
(Note 5) 300 ns
Capacitive Load for each Bus
Line
C
B
400 pF
SDA AND SCL I/O STAGE CHARACTERISTICS
Input-Voltage Low V
IL
0.3 x
V
L
V
Input-Voltage High V
IH
0.7 x
V
L
V
SDA Output-Voltage Low V
OL
I
SINK
= 3mA 0.4 V
Pulse Width of Suppressed Spike t
SP
(Note 6) 50 ns
Note 2: Parameters are 100% production tested at +25°C. Limits over temperature are guaranteed by design.
Note 3: Guaranteed by bench characterization. Limits are not production tested.
Note 4: A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL’s falling
edge.
Note 5: C
B
is the total capacitance of one bus line in pF, tested with C
B
= 400pF.
Note 6: Input filters on SDA, SCL, and ADD suppress noise spikes of less than 50ns.
SMBus is a trademark of Intel Corporation.