Datasheet

addressed at I
2
C register location 10h, 11h (as well as
locations 16h, 17h) to support USB OTG SIE implemen-
tations that are limited to I
2
C register addresses
between 0h and 15h.
ID and Manufacturer Register Address Map
Table 17 provides the contents of the ID registers of the
MAX3301E/MAX3302E. Addresses 00h and 01h com-
prise the vendor ID registers. Addresses 02h and 03h
comprise the product ID registers. Addresses 14h and
15h comprise the revision ID registers.
Audio Car Kit
Many cell phones are required to interface to car kits.
Depending upon the car kit, the interface to the phone
may be required to support any or all of the following
functions:
• Audio input
• Audio output
• Charging
• Control and status
D+ and D- of the MAX3301E/MAX3302E go to a high-
impedance state when in shutdown mode, allowing
external signals (including audio) to be multiplexed onto
these lines.
External Components
External Resistors
Two external resistors (27.4Ω ±1%) are required for
USB connection. Install one resistor in series between
D+ of the MAX3301E/MAX3302E and D+ of the USB
connector. Install the other resistor in series between D-
of the MAX3301E/MAX3302E and D- of the USB con-
nector (see the
Typical Operating Circuit ).
External Capacitors
Five external capacitors are recommended for proper
operation. Install all capacitors as close to the device as
possible. Decouple V
L
to GND with a 0.1µF ceramic
capacitor. Bypass V
CC
to GND with a 1µF ceramic
capacitor. Bypass TRM to GND with a 1µF (or greater)
ceramic or plastic capacitor. Connect a 100nF flying
capacitor between C+ and C- for the charge pump (see
the Typical Operating Circuit ). Bypass V
BUS
to GND
with a 1µF to 6.5µF ceramic capacitor in accordance
with USB OTG specifications.
ESD Protection
To protect the MAX3301E/MAX3302E against ESD, D+,
D-, ID_IN, and V
BUS
, have extra protection against stat-
ic electricity to protect the device up to ±15kV. The ESD
structures withstand high ESD in all states; normal oper-
MAX3301E/MAX3302E
USB On-the-Go Transceivers and Charge Pumps
26 ______________________________________________________________________________________
BIT NUMBER SYMBOL CONTENTS
VALUE AT
POWER-UP
0 vbus_vld
S et to 0 to d i sab l e the vb us_vld i nter rup t for a l ow - to- hi gh transiti on. S et to 1 to
enab l e the vb us_vld i nter rup t for a l ow - to- hi gh transiti on. S ee Tab l es 10 and 11.
0
1 sess_vld
S et to 0 to d i sab l e the sess_vld i nter rup t for a l ow - to- hi gh transiti on. S et to 1 to
enab l e the sess_vld i nter rup t for a l ow - to- hi gh transiti on. S ee Tab l es 10 and 11.
0
2 dp_hi
S et to 0 to d i sab l e the d p _hi i nter r up t for a l ow - to- hi g h tr ansi ti on. S et to 1 to
enab l e the d p _hi i nter r up t for a l ow - to- hi g h tr ansi ti on. S ee Tab l es 10 and 11.
0
3 id_gnd
S et to 0 to d i sab l e the i d _g nd i nter r up t for a l ow - to- hi g h tr ansi ti on. S et to 1 to
enab l e the i d _g nd i nter r up t for a l ow - to- hi g h tr ansi ti on. S ee Tab l es 10 and 11.
0
4 dm_hi
S et to 0 to d i sab l e the d m _hi i nter r up t for a l ow - to- hi g h tr ansi ti on. S et to 1 to
enab l e the d m _hi i nter r up t for a l ow - to- hi g h tr ansi ti on. S ee Tab l es 10 and 11.
0
5 id_float
S et to 0 to d i sab l e the i d _fl oat i nter r up t for a l ow - to- hi g h tr ansi ti on. S et to 1 to
enab l e the i d _fl oat i nter r up t for a l ow - to- hi g h tr ansi ti on. S ee Tab l es 10 and 11.
0
6 bdis_acon
S et to 0 to d i sab l e the b d is_acon interr up t for a low - to- hig h tr ansi ti on. Set to 1 to
enab l e the b d is_acon interr up t for a low - to- hig h tr ansi ti on. See Tab l es 10 and 11.
0
7 cr_int_sess_end
S et to 0 to d i sab l e the cr _i nt_sess_end i nter r up t for a l ow - to- hi g h tr ansi ti on.
S et to 1 to enab l e the cr _i nt_sess_end i nter r up t for a l ow - to- hi g h tr ansi ti on.
S ee Tab l es 10 and 11.
0
Table 13. Interrupt-Enable High Register (Write to Address 0Eh to Set, Write to Address
0Fh to Clear)