Datasheet

MAX3301E/MAX3302E
USB On-the-Go Transceivers and Charge Pumps
10 ______________________________________________________________________________________
Pin Description (continued)
PIN
MAX3302E
28-PIN TQFN
MAX3301E
32-PIN TQFN
UCSP/
WLP
NAME FUNCTION
15 18 B4 INT
Active-Low Interrupt Source. Program the INT output as push-pull or open-
drain with the irq_mode bit (bit 1 of special-function register 2, see Tables 15
and 16).
16 19 B5 RESET
Active-Low Reset Input. Drive RESET low to asynchronously reset the
MAX3301E/MAX3302E.
17 20 C3 ADD I
2
C-Interface Address Selection Input. (See Table 5.)
19 22 C4 ID_IN
ID Input. ID_IN is internally pulled up to V
CC
. The state of ID_IN determines
ID bits 3 and 5 of the interrupt source register (see Table 10).
20 23 D5 D-
USB Differential Data Input/Output. Connect D- to the D- terminal of the USB
connector through a 27.4Ω ±1% series resistor.
21 24 E5 D+
USB Differential Data Input/Output. Connect D+ to the D+ terminal of the USB
connector through a 27.4Ω ±1% series resistor.
22 26 D4 VM
Single-Ended Receiver Output. VM functions as a receiver output in all
operating modes. VM duplicates D-.
24 27 E4 TRM
USB Transceiver Regulated Output Voltage. TRM provides a regulated 3.3V
output. Bypass TRM to GND with a 1µF ceramic capacitor installed as close
to the device as possible. TRM normally derives power from V
CC
. TRM
provides power to internal circuitry and provides the pullup voltage for the
internal USB pullup resistor. Do not use TRM to power external circuitry. The
reg_sel bit (bit 3 of special-function register 2, see Table 15 and Table 16)
controls the TRM power source with software.
26 30 D3 VP
Single-Ended Receiver Output. VP functions as a receiver output in all
operating modes. VP duplicates D+.
27 31 E2 V
BUS
USB Bus Power. Use V
BUS
as an output to power the USB bus, or as an input
to power the internal linear regulator. Bits 5 to 7 of control register 2 (see
Table 8) control the charging and discharging functions of V
BUS
.
28 32 E1 C+ Charge-Pump Flying-Capacitor Positive Terminal
EP EP — EP Exposed Paddle. Connect EP to GND or leave unconnected.
Test Circuits and Timing Diagrams
DUT
27.4Ω 220Ω
TEST POINT
C
L
V
D+/D-
LOAD FOR DISABLE TIME (D+/D-) MEASUREMENT
V = 0 FOR t
PHZ
.
V = V
TRM
FOR t
PLZ
.
C
L
= 50pF FOR FULL SPEED.
C
L
= 200pF TO 600pF FOR LOW SPEED.
Figure 1. Load for Disable Time Measurement
DUT
27.4Ω
15kΩ
TEST POINT
C
L
D+/D-
LOAD FOR
1) ENABLE TIME (D+/D-) MEASUREMENT
2) DAT_VP/SEO_VM TO D+/D- PROPAGATION DELAY
3) D+/D- RISE/FALL TIMES
C
L
= 50pF FOR FULL SPEED.
C
L
= 200pF TO 600pF FOR LOW SPEED.
Figure 2. Load for Enable Time, Transmitter Propagation Delay,
and Transmitter Rise/Fall Times